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Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +00001/*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Padmavathi Venna <padma.v@samsung.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +00006 */
7
8#include <common.h>
Simon Glass73186c92014-10-13 23:42:01 -06009#include <dm.h>
10#include <errno.h>
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000011#include <malloc.h>
12#include <spi.h>
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +000013#include <fdtdec.h>
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000014#include <asm/arch/clk.h>
15#include <asm/arch/clock.h>
16#include <asm/arch/cpu.h>
17#include <asm/arch/gpio.h>
18#include <asm/arch/pinmux.h>
19#include <asm/arch-exynos/spi.h>
20#include <asm/io.h>
21
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +000022DECLARE_GLOBAL_DATA_PTR;
23
Simon Glass73186c92014-10-13 23:42:01 -060024struct exynos_spi_platdata {
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000025 enum periph_id periph_id;
26 s32 frequency; /* Default clock frequency, -1 for none */
27 struct exynos_spi *regs;
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +053028 uint deactivate_delay_us; /* Delay to wait after deactivate */
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000029};
30
Simon Glass73186c92014-10-13 23:42:01 -060031struct exynos_spi_priv {
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000032 struct exynos_spi *regs;
33 unsigned int freq; /* Default frequency */
34 unsigned int mode;
35 enum periph_id periph_id; /* Peripheral ID for this device */
36 unsigned int fifo_size;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +000037 int skip_preamble;
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +053038 ulong last_transaction_us; /* Time of last transaction end */
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000039};
40
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000041/**
42 * Flush spi tx, rx fifos and reset the SPI controller
43 *
Simon Glass73186c92014-10-13 23:42:01 -060044 * @param regs Pointer to SPI registers
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000045 */
Simon Glass73186c92014-10-13 23:42:01 -060046static void spi_flush_fifo(struct exynos_spi *regs)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000047{
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000048 clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
49 clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
50 setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
51}
52
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000053static void spi_get_fifo_levels(struct exynos_spi *regs,
54 int *rx_lvl, int *tx_lvl)
55{
56 uint32_t spi_sts = readl(&regs->spi_sts);
57
58 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
59 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
60}
61
62/**
63 * If there's something to transfer, do a software reset and set a
64 * transaction size.
65 *
66 * @param regs SPI peripheral registers
67 * @param count Number of bytes to transfer
Rajeshwari Shindec4a79632013-10-08 16:20:06 +053068 * @param step Number of bytes to transfer in each packet (1 or 4)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000069 */
Rajeshwari Shindec4a79632013-10-08 16:20:06 +053070static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000071{
Simon Glass73186c92014-10-13 23:42:01 -060072 debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
73
Rajeshwari Shindec4a79632013-10-08 16:20:06 +053074 /* For word address we need to swap bytes */
75 if (step == 4) {
76 setbits_le32(&regs->mode_cfg,
77 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
78 count /= 4;
79 setbits_le32(&regs->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
80 SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
81 SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
82 } else {
83 /* Select byte access and clear the swap configuration */
84 clrbits_le32(&regs->mode_cfg,
85 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
86 writel(0, &regs->swap_cfg);
87 }
88
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000089 assert(count && count < (1 << 16));
90 setbits_le32(&regs->ch_cfg, SPI_CH_RST);
91 clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
Rajeshwari Shindec4a79632013-10-08 16:20:06 +053092
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000093 writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
94}
95
Simon Glass73186c92014-10-13 23:42:01 -060096static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +000097 void **dinp, void const **doutp, unsigned long flags)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000098{
Simon Glass73186c92014-10-13 23:42:01 -060099 struct exynos_spi *regs = priv->regs;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000100 uchar *rxp = *dinp;
101 const uchar *txp = *doutp;
102 int rx_lvl, tx_lvl;
103 uint out_bytes, in_bytes;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000104 int toread;
105 unsigned start = get_timer(0);
106 int stopping;
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530107 int step;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000108
109 out_bytes = in_bytes = todo;
110
Simon Glass73186c92014-10-13 23:42:01 -0600111 stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
112 !(priv->mode & SPI_SLAVE);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000113
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000114 /*
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530115 * Try to transfer words if we can. This helps read performance at
116 * SPI clock speeds above about 20MHz.
117 */
118 step = 1;
119 if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
Simon Glass73186c92014-10-13 23:42:01 -0600120 !priv->skip_preamble)
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530121 step = 4;
122
123 /*
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000124 * If there's something to send, do a software reset and set a
125 * transaction size.
126 */
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530127 spi_request_bytes(regs, todo, step);
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000128
129 /*
130 * Bytes are transmitted/received in pairs. Wait to receive all the
131 * data because then transmission will be done as well.
132 */
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000133 toread = in_bytes;
134
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000135 while (in_bytes) {
136 int temp;
137
138 /* Keep the fifos full/empty. */
139 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530140
141 /*
142 * Don't completely fill the txfifo, since we don't want our
143 * rxfifo to overflow, and it may already contain data.
144 */
Simon Glass73186c92014-10-13 23:42:01 -0600145 while (tx_lvl < priv->fifo_size/2 && out_bytes) {
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530146 if (!txp)
147 temp = -1;
148 else if (step == 4)
149 temp = *(uint32_t *)txp;
150 else
151 temp = *txp;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000152 writel(temp, &regs->tx_data);
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530153 out_bytes -= step;
154 if (txp)
155 txp += step;
156 tx_lvl += step;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000157 }
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530158 if (rx_lvl >= step) {
159 while (rx_lvl >= step) {
Rajeshwari Shinde120af152013-10-08 16:20:05 +0530160 temp = readl(&regs->rx_data);
Simon Glass73186c92014-10-13 23:42:01 -0600161 if (priv->skip_preamble) {
Rajeshwari Shinde120af152013-10-08 16:20:05 +0530162 if (temp == SPI_PREAMBLE_END_BYTE) {
Simon Glass73186c92014-10-13 23:42:01 -0600163 priv->skip_preamble = 0;
Rajeshwari Shinde120af152013-10-08 16:20:05 +0530164 stopping = 0;
165 }
166 } else {
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530167 if (rxp || stopping) {
Akshay Saraswate76d2a82014-06-18 17:52:41 +0530168 if (step == 4)
169 *(uint32_t *)rxp = temp;
170 else
171 *rxp = temp;
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530172 rxp += step;
173 }
174 in_bytes -= step;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000175 }
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530176 toread -= step;
177 rx_lvl -= step;
178 }
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000179 } else if (!toread) {
180 /*
181 * We have run out of input data, but haven't read
182 * enough bytes after the preamble yet. Read some more,
183 * and make sure that we transmit dummy bytes too, to
184 * keep things going.
185 */
186 assert(!out_bytes);
187 out_bytes = in_bytes;
188 toread = in_bytes;
189 txp = NULL;
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530190 spi_request_bytes(regs, toread, step);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000191 }
Simon Glass73186c92014-10-13 23:42:01 -0600192 if (priv->skip_preamble && get_timer(start) > 100) {
Simon Glassc7d50e72015-07-02 18:16:11 -0600193 debug("SPI timeout: in_bytes=%d, out_bytes=%d, ",
194 in_bytes, out_bytes);
195 return -ETIMEDOUT;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000196 }
197 }
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000198
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000199 *dinp = rxp;
200 *doutp = txp;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000201
202 return 0;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000203}
204
205/**
Simon Glass73186c92014-10-13 23:42:01 -0600206 * Activate the CS by driving it LOW
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000207 *
Simon Glass73186c92014-10-13 23:42:01 -0600208 * @param slave Pointer to spi_slave to which controller has to
209 * communicate with
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000210 */
Simon Glass73186c92014-10-13 23:42:01 -0600211static void spi_cs_activate(struct udevice *dev)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000212{
Simon Glass73186c92014-10-13 23:42:01 -0600213 struct udevice *bus = dev->parent;
214 struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
215 struct exynos_spi_priv *priv = dev_get_priv(bus);
216
217 /* If it's too soon to do another transaction, wait */
218 if (pdata->deactivate_delay_us &&
219 priv->last_transaction_us) {
220 ulong delay_us; /* The delay completed so far */
221 delay_us = timer_get_us() - priv->last_transaction_us;
222 if (delay_us < pdata->deactivate_delay_us)
223 udelay(pdata->deactivate_delay_us - delay_us);
224 }
225
226 clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
227 debug("Activate CS, bus '%s'\n", bus->name);
228 priv->skip_preamble = priv->mode & SPI_PREAMBLE;
229}
230
231/**
232 * Deactivate the CS by driving it HIGH
233 *
234 * @param slave Pointer to spi_slave to which controller has to
235 * communicate with
236 */
237static void spi_cs_deactivate(struct udevice *dev)
238{
239 struct udevice *bus = dev->parent;
240 struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
241 struct exynos_spi_priv *priv = dev_get_priv(bus);
242
243 setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
244
245 /* Remember time of this transaction so we can honour the bus delay */
246 if (pdata->deactivate_delay_us)
247 priv->last_transaction_us = timer_get_us();
248
249 debug("Deactivate CS, bus '%s'\n", bus->name);
250}
251
252static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
253{
254 struct exynos_spi_platdata *plat = bus->platdata;
255 const void *blob = gd->fdt_blob;
256 int node = bus->of_offset;
257
258 plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
259 plat->periph_id = pinmux_decode_periph_id(blob, node);
260
261 if (plat->periph_id == PERIPH_ID_NONE) {
262 debug("%s: Invalid peripheral ID %d\n", __func__,
263 plat->periph_id);
264 return -FDT_ERR_NOTFOUND;
265 }
266
267 /* Use 500KHz as a suitable default */
268 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
269 500000);
270 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
271 "spi-deactivate-delay", 0);
272 debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
273 __func__, plat->regs, plat->periph_id, plat->frequency,
274 plat->deactivate_delay_us);
275
276 return 0;
277}
278
279static int exynos_spi_probe(struct udevice *bus)
280{
281 struct exynos_spi_platdata *plat = dev_get_platdata(bus);
282 struct exynos_spi_priv *priv = dev_get_priv(bus);
283
284 priv->regs = plat->regs;
285 if (plat->periph_id == PERIPH_ID_SPI1 ||
286 plat->periph_id == PERIPH_ID_SPI2)
287 priv->fifo_size = 64;
288 else
289 priv->fifo_size = 256;
290
291 priv->skip_preamble = 0;
292 priv->last_transaction_us = timer_get_us();
293 priv->freq = plat->frequency;
294 priv->periph_id = plat->periph_id;
295
296 return 0;
297}
298
Simon Glass9694b722015-04-19 09:05:40 -0600299static int exynos_spi_claim_bus(struct udevice *dev)
Simon Glass73186c92014-10-13 23:42:01 -0600300{
Simon Glass9694b722015-04-19 09:05:40 -0600301 struct udevice *bus = dev->parent;
Simon Glass73186c92014-10-13 23:42:01 -0600302 struct exynos_spi_priv *priv = dev_get_priv(bus);
303
304 exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
305 spi_flush_fifo(priv->regs);
306
307 writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
308
309 return 0;
310}
311
Simon Glass9694b722015-04-19 09:05:40 -0600312static int exynos_spi_release_bus(struct udevice *dev)
Simon Glass73186c92014-10-13 23:42:01 -0600313{
Simon Glass9694b722015-04-19 09:05:40 -0600314 struct udevice *bus = dev->parent;
Simon Glass73186c92014-10-13 23:42:01 -0600315 struct exynos_spi_priv *priv = dev_get_priv(bus);
316
317 spi_flush_fifo(priv->regs);
318
319 return 0;
320}
321
322static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
323 const void *dout, void *din, unsigned long flags)
324{
325 struct udevice *bus = dev->parent;
326 struct exynos_spi_priv *priv = dev_get_priv(bus);
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000327 int upto, todo;
328 int bytelen;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000329 int ret = 0;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000330
331 /* spi core configured to do 8 bit transfers */
332 if (bitlen % 8) {
333 debug("Non byte aligned SPI transfer.\n");
334 return -1;
335 }
336
337 /* Start the transaction, if necessary. */
338 if ((flags & SPI_XFER_BEGIN))
Simon Glass73186c92014-10-13 23:42:01 -0600339 spi_cs_activate(dev);
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000340
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530341 /*
342 * Exynos SPI limits each transfer to 65535 transfers. To keep
343 * things simple, allow a maximum of 65532 bytes. We could allow
344 * more in word mode, but the performance difference is small.
345 */
Simon Glass73186c92014-10-13 23:42:01 -0600346 bytelen = bitlen / 8;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000347 for (upto = 0; !ret && upto < bytelen; upto += todo) {
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530348 todo = min(bytelen - upto, (1 << 16) - 4);
Simon Glass73186c92014-10-13 23:42:01 -0600349 ret = spi_rx_tx(priv, todo, &din, &dout, flags);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000350 if (ret)
351 break;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000352 }
353
354 /* Stop the transaction, if necessary. */
Simon Glass73186c92014-10-13 23:42:01 -0600355 if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
356 spi_cs_deactivate(dev);
357 if (priv->skip_preamble) {
358 assert(!priv->skip_preamble);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000359 debug("Failed to complete premable transaction\n");
360 ret = -1;
361 }
362 }
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000363
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000364 return ret;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000365}
366
Simon Glass73186c92014-10-13 23:42:01 -0600367static int exynos_spi_set_speed(struct udevice *bus, uint speed)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000368{
Simon Glass73186c92014-10-13 23:42:01 -0600369 struct exynos_spi_platdata *plat = bus->platdata;
370 struct exynos_spi_priv *priv = dev_get_priv(bus);
371 int ret;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000372
Simon Glass73186c92014-10-13 23:42:01 -0600373 if (speed > plat->frequency)
374 speed = plat->frequency;
375 ret = set_spi_clk(priv->periph_id, speed);
376 if (ret)
377 return ret;
378 priv->freq = speed;
379 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000380
381 return 0;
382}
383
Simon Glass73186c92014-10-13 23:42:01 -0600384static int exynos_spi_set_mode(struct udevice *bus, uint mode)
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000385{
Simon Glass73186c92014-10-13 23:42:01 -0600386 struct exynos_spi_priv *priv = dev_get_priv(bus);
387 uint32_t reg;
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000388
Simon Glass73186c92014-10-13 23:42:01 -0600389 reg = readl(&priv->regs->ch_cfg);
390 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000391
Simon Glass73186c92014-10-13 23:42:01 -0600392 if (mode & SPI_CPHA)
393 reg |= SPI_CH_CPHA_B;
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000394
Simon Glass73186c92014-10-13 23:42:01 -0600395 if (mode & SPI_CPOL)
396 reg |= SPI_CH_CPOL_L;
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000397
Simon Glass73186c92014-10-13 23:42:01 -0600398 writel(reg, &priv->regs->ch_cfg);
399 priv->mode = mode;
400 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000401
402 return 0;
403}
404
Simon Glass73186c92014-10-13 23:42:01 -0600405static const struct dm_spi_ops exynos_spi_ops = {
406 .claim_bus = exynos_spi_claim_bus,
407 .release_bus = exynos_spi_release_bus,
408 .xfer = exynos_spi_xfer,
409 .set_speed = exynos_spi_set_speed,
410 .set_mode = exynos_spi_set_mode,
411 /*
412 * cs_info is not needed, since we require all chip selects to be
413 * in the device tree explicitly
414 */
415};
Hung-ying Tyanf3424c52013-05-15 18:27:30 +0800416
Simon Glass73186c92014-10-13 23:42:01 -0600417static const struct udevice_id exynos_spi_ids[] = {
418 { .compatible = "samsung,exynos-spi" },
419 { }
420};
Hung-ying Tyanf3424c52013-05-15 18:27:30 +0800421
Simon Glass73186c92014-10-13 23:42:01 -0600422U_BOOT_DRIVER(exynos_spi) = {
423 .name = "exynos_spi",
424 .id = UCLASS_SPI,
425 .of_match = exynos_spi_ids,
426 .ops = &exynos_spi_ops,
427 .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
428 .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
429 .priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
Simon Glass73186c92014-10-13 23:42:01 -0600430 .probe = exynos_spi_probe,
431};