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Michael Schwingenaebf00f2008-01-16 19:51:14 +01001/*
2 * (C) Copyright 2007
3 * Michael Schwingen, michael@schwingen.org
4 *
5 * Configuration settings for the AcTux-2 board.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#define CONFIG_IXP425 1
30#define CONFIG_ACTUX2 1
31
Marek Vasut8e807ec2012-03-06 00:45:35 +010032#define CONFIG_MACH_TYPE 1480
33
Michael Schwingenaebf00f2008-01-16 19:51:14 +010034#define CONFIG_DISPLAY_CPUINFO 1
35#define CONFIG_DISPLAY_BOARDINFO 1
36
Jean-Christophe PLAGNIOL-VILLARD930590f2009-01-31 09:10:48 +010037#define CONFIG_IXP_SERIAL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
Michael Schwingenaebf00f2008-01-16 19:51:14 +010039#define CONFIG_BAUDRATE 115200
40#define CONFIG_BOOTDELAY 5
41#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
Michael Schwingenaf050482011-05-23 00:00:05 +020042#define CONFIG_BOARD_EARLY_INIT_F 1
43#define CONFIG_SYS_LDSCRIPT "board/actux2/u-boot.lds"
Michael Schwingenaebf00f2008-01-16 19:51:14 +010044
45/***************************************************************
46 * U-boot generic defines start here.
47 ***************************************************************/
Michael Schwingenaebf00f2008-01-16 19:51:14 +010048/* Size of malloc() pool */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
Michael Schwingenaebf00f2008-01-16 19:51:14 +010050
51/* allow to overwrite serial and ethaddr */
52#define CONFIG_ENV_OVERWRITE
53
54/* Command line configuration. */
55#include <config_cmd_default.h>
56
57#define CONFIG_CMD_ELF
58#undef CONFIG_CMD_PCI
59#undef CONFIG_PCI
60
61#define CONFIG_BOOTCOMMAND "run boot_flash"
62/* enable passing of ATAGs */
63#define CONFIG_CMDLINE_TAG 1
64#define CONFIG_SETUP_MEMORY_TAGS 1
65#define CONFIG_INITRD_TAG 1
66#define CONFIG_REVISION_TAG 1
67
68#if defined(CONFIG_CMD_KGDB)
69# define CONFIG_KGDB_BAUDRATE 230400
70/* which serial port to use */
71# define CONFIG_KGDB_SER_INDEX 1
72#endif
73
74/* Miscellaneous configurable options */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_LONGHELP
76#define CONFIG_SYS_PROMPT "=> "
Michael Schwingenaebf00f2008-01-16 19:51:14 +010077/* Console I/O Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_CBSIZE 256
Michael Schwingenaebf00f2008-01-16 19:51:14 +010079/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
Michael Schwingenaebf00f2008-01-16 19:51:14 +010081/* max number of command args */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_MAXARGS 16
Michael Schwingenaebf00f2008-01-16 19:51:14 +010083/* Boot Argument Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Michael Schwingenaebf00f2008-01-16 19:51:14 +010085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_MEMTEST_START 0x00400000
87#define CONFIG_SYS_MEMTEST_END 0x00800000
Michael Schwingenaebf00f2008-01-16 19:51:14 +010088
Michael Schwingenaf050482011-05-23 00:00:05 +020089/* timer clock - 2* OSC_IN system clock */
90#define CONFIG_IXP425_TIMER_CLK 66666666
91#define CONFIG_SYS_HZ 1000
Michael Schwingenaebf00f2008-01-16 19:51:14 +010092
93/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_LOAD_ADDR 0x00010000
Michael Schwingenaebf00f2008-01-16 19:51:14 +010095
96/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
Michael Schwingenaebf00f2008-01-16 19:51:14 +010098 115200, 230400 }
99#define CONFIG_SERIAL_RTS_ACTIVE 1
100
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100101/* Expansion bus settings */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_EXP_CS0 0xbd113042
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100103
104/* SDRAM settings */
105#define CONFIG_NR_DRAM_BANKS 1
106#define PHYS_SDRAM_1 0x00000000
Michael Schwingenaf050482011-05-23 00:00:05 +0200107#define CONFIG_SYS_SDRAM_BASE 0x00000000
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100108
109/* 16MB SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_SDR_CONFIG 0x3A
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100111#define PHYS_SDRAM_1_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
113#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
114#define CONFIG_SYS_DRAM_SIZE 0x01000000
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100115
116/* FLASH organization */
Michael Schwingenaf050482011-05-23 00:00:05 +0200117#define CONFIG_SYS_TEXT_BASE 0x50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MAX_FLASH_BANKS 1
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100119/* max number of sectors on one chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_MAX_FLASH_SECT 140
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100121#define PHYS_FLASH_1 0x50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
125#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
126#define CONFIG_SYS_MONITOR_LEN (256 << 10)
Michael Schwingenaf050482011-05-23 00:00:05 +0200127#define CONFIG_BOARD_SIZE_LIMIT 262144
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100128
129/* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200131#define CONFIG_FLASH_CFI_DRIVER
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100132/* no byte writes on IXP4xx */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100134
135/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_FLASH_EMPTY_INFO
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100137
138/* Ethernet */
139
140/* include IXP4xx NPE support */
141#define CONFIG_IXP4XX_NPE 1
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100142/* NPE0 PHY address */
143#define CONFIG_PHY_ADDR 0x00
144/* MII PHY management */
145#define CONFIG_MII 1
Michael Schwingenaf050482011-05-23 00:00:05 +0200146/* fixed-speed switch without standard PHY registers on MII */
147#define CONFIG_MII_NPE0_FIXEDLINK 1
148#define CONFIG_MII_NPE0_SPEED 100
149#define CONFIG_MII_NPE0_FULLDUPLEX 1
150
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100151/* Number of ethernet rx buffers & descriptors */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_RX_ETH_BUFFER 16
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100153#define CONFIG_RESET_PHY_R 1
154/* ethernet switch connected to MII port */
155#define CONFIG_MII_ETHSWITCH 1
156
157#define CONFIG_CMD_DHCP
158#define CONFIG_CMD_NET
159#define CONFIG_CMD_MII
160#define CONFIG_CMD_PING
161#undef CONFIG_CMD_NFS
162
163/* BOOTP options */
164#define CONFIG_BOOTP_BOOTFILESIZE
165#define CONFIG_BOOTP_BOOTPATH
166#define CONFIG_BOOTP_GATEWAY
167#define CONFIG_BOOTP_HOSTNAME
168
169/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_CACHELINE_SIZE 32
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100171
172/*
173 * environment organization:
174 * one flash sector, embedded in uboot area (bottom bootblock flash)
175 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200176#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200177#define CONFIG_ENV_SIZE 0x2000
178#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_USE_PPCENV 1
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100180
181#define CONFIG_EXTRA_ENV_SETTINGS \
Jean-Christophe PLAGNIOL-VILLARDb4e2f892009-01-31 09:53:39 +0100182 "npe_ucode=50040000\0" \
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100183 "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
184 "kerneladdr=50050000\0" \
Michael Schwingenaf050482011-05-23 00:00:05 +0200185 "kernelfile=actux2/uImage\0" \
186 "rootfile=actux2/rootfs\0" \
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100187 "rootaddr=50170000\0" \
188 "loadaddr=10000\0" \
189 "updateboot_ser=mw.b 10000 ff 40000;" \
190 " loady ${loadaddr};" \
191 " run eraseboot writeboot\0" \
192 "updateboot_net=mw.b 10000 ff 40000;" \
Michael Schwingenaf050482011-05-23 00:00:05 +0200193 " tftp ${loadaddr} actux2/u-boot.bin;" \
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100194 " run eraseboot writeboot\0" \
195 "eraseboot=protect off 50000000 50003fff;" \
196 " protect off 50006000 5003ffff;" \
197 " erase 50000000 50003fff;" \
198 " erase 50006000 5003ffff\0" \
199 "writeboot=cp.b 10000 50000000 4000;" \
200 " cp.b 16000 50006000 3a000\0" \
Michael Schwingenaf050482011-05-23 00:00:05 +0200201 "updateucode=loady;" \
202 " era ${npe_ucode} +${filesize};" \
203 " cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100204 "updateroot=tftp ${loadaddr} ${rootfile};" \
205 " era ${rootaddr} +${filesize};" \
206 " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
207 "updatekern=tftp ${loadaddr} ${kernelfile};" \
208 " era ${kerneladdr} +${filesize};" \
209 " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
210 "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
211 " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
212 "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
213 " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
214 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
215 "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
216 "boot_flash=run flashargs addtty addeth;" \
217 " bootm ${kerneladdr}\0" \
218 "boot_net=run netargs addtty addeth;" \
219 " tftpboot ${loadaddr} ${kernelfile};" \
220 " bootm\0"
221
Michael Schwingenaf050482011-05-23 00:00:05 +0200222/* additions for new relocation code, must be added to all boards */
223#define CONFIG_SYS_INIT_SP_ADDR \
224 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
225
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100226#endif /* __CONFIG_H */