blob: 6c462af53ccafc2b979d82c8bab674c233dc7271 [file] [log] [blame]
Heiko Schocherfa230442006-12-21 17:17:02 +01001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37#define CONFIG_MPC8272_FAMILY 1
38#define CONFIG_TQM8272 1
39
40#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +010041#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
42
Heiko Schocherfa230442006-12-21 17:17:02 +010043#define STK82xx_150 1 /* on a STK82xx.150 */
44
45#define CONFIG_CPM2 1 /* Has a CPM2 */
46
47#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
48
49#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
50
51#define CONFIG_BOARD_EARLY_INIT_R 1
52
53#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
54#define CONFIG_BAUDRATE 230400
55#else
56#define CONFIG_BAUDRATE 115200
57#endif
58
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010059#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
Heiko Schocherfa230442006-12-21 17:17:02 +010060
61#undef CONFIG_BOOTARGS
62
63#define CONFIG_EXTRA_ENV_SETTINGS \
64 "netdev=eth0\0" \
65 "consdev=ttyCPM0\0" \
66 "nfsargs=setenv bootargs root=/dev/nfs rw " \
67 "nfsroot=${serverip}:${rootpath}\0" \
68 "ramargs=setenv bootargs root=/dev/ram rw\0" \
69 "hostname=tqm8272\0" \
70 "addip=setenv bootargs ${bootargs} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
72 ":${hostname}:${netdev}:off panic=1\0" \
73 "addcons=setenv bootargs ${bootargs} " \
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +010074 "console=$(consdev),$(baudrate)\0" \
75 "flash_nfs=run nfsargs addip addcons;" \
Heiko Schocherfa230442006-12-21 17:17:02 +010076 "bootm ${kernel_addr}\0" \
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +010077 "flash_self=run ramargs addip addcons;" \
Heiko Schocherfa230442006-12-21 17:17:02 +010078 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
79 "net_nfs=tftp 300000 ${bootfile};" \
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +010080 "run nfsargs addip addcons;bootm\0" \
Heiko Schocherfa230442006-12-21 17:17:02 +010081 "rootpath=/opt/eldk/ppc_82xx\0" \
82 "bootfile=/tftpboot/tqm8272/uImage\0" \
83 "kernel_addr=40080000\0" \
84 "ramdisk_addr=40100000\0" \
85 "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \
86 "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \
87 "cp.b 300000 40000000 40000;" \
88 "setenv filesize;saveenv\0" \
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +010089 "cphwib=cp.b 4003fc00 33fc00 400\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +010090 "upd=run load cphwib update\0" \
Heiko Schocherfa230442006-12-21 17:17:02 +010091 ""
92#define CONFIG_BOOTCOMMAND "run flash_self"
93
94#define CONFIG_I2C 1
95
96#if CONFIG_I2C
97/* enable I2C and select the hardware/software driver */
98#undef CONFIG_HARD_I2C /* I2C with hardware support */
99#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
101#define CONFIG_SYS_I2C_SLAVE 0x7F
Heiko Schocherfa230442006-12-21 17:17:02 +0100102
103/*
104 * Software (bit-bang) I2C driver configuration
105 */
106#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
107#define I2C_ACTIVE (iop->pdir |= 0x00010000)
108#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
109#define I2C_READ ((iop->pdat & 0x00010000) != 0)
110#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
111 else iop->pdat &= ~0x00010000
112#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
113 else iop->pdat &= ~0x00020000
114#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
115
116#define CONFIG_I2C_X
117
118/* EEPROM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
120#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
121#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
122#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
Heiko Schocherfa230442006-12-21 17:17:02 +0100123
124/* I2C RTC */
125#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100127
128/* I2C SYSMON (LM75) */
129#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
130#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_DTT_MAX_TEMP 70
132#define CONFIG_SYS_DTT_LOW_TEMP -30
133#define CONFIG_SYS_DTT_HYSTERESIS 3
Heiko Schocherfa230442006-12-21 17:17:02 +0100134
135#else
136#undef CONFIG_HARD_I2C
137#undef CONFIG_SOFT_I2C
Heiko Schocherfa230442006-12-21 17:17:02 +0100138#endif
139
140/*
141 * select serial console configuration
142 *
143 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
144 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
145 * for SCC).
146 *
147 * if CONFIG_CONS_NONE is defined, then the serial console routines must
148 * defined elsewhere (for example, on the cogent platform, there are serial
149 * ports on the motherboard which are used for the serial console - see
150 * cogent/cma101/serial.[ch]).
151 */
152#define CONFIG_CONS_ON_SMC /* define if console on SMC */
153#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
154#undef CONFIG_CONS_NONE /* define if console on something else*/
155#ifdef CONFIG_82xx_CONS_SMC1
156#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
157#endif
158#ifdef CONFIG_82xx_CONS_SMC2
159#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
160#endif
161
162#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
163#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
164#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
165
166/*
167 * select ethernet configuration
168 *
169 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
170 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
171 * for FCC)
172 *
173 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500174 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
Heiko Schocherfa230442006-12-21 17:17:02 +0100175 *
176 * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
177 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_FCC_ETHERNET
Heiko Schocherfa230442006-12-21 17:17:02 +0100180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#if defined(CONFIG_SYS_FCC_ETHERNET)
Heiko Schocherfa230442006-12-21 17:17:02 +0100182#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
183#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
184#undef CONFIG_ETHER_NONE /* define if ether on something else */
185#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
186#else
187#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */
188#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
189#undef CONFIG_ETHER_NONE /* define if ether on something else */
190#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
191#endif
192
193#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
194
195/*
196 * - RX clk is CLK11
197 * - TX clk is CLK12
198 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
Heiko Schocherfa230442006-12-21 17:17:02 +0100200
201#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
202
203/*
204 * - Rx-CLK is CLK13
205 * - Tx-CLK is CLK14
206 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
207 * - Enable Full Duplex in FSMR
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
210# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
211# define CONFIG_SYS_CPMFCR_RAMTYPE 0
212# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
Heiko Schocherfa230442006-12-21 17:17:02 +0100213
214#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
215
216#define CONFIG_MII /* MII PHY management */
217#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
218/*
219 * GPIO pins used for bit-banged MII communications
220 */
221#define MDIO_PORT 2 /* Port C */
222
223#if STK82xx_150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */
225#define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100226#endif
227
228#if STK82xx_100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */
230#define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100231#endif
232
233#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
235#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
236#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
Heiko Schocherfa230442006-12-21 17:17:02 +0100237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
239 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
Heiko Schocherfa230442006-12-21 17:17:02 +0100240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
242 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
Heiko Schocherfa230442006-12-21 17:17:02 +0100243#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
245#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
246#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
Heiko Schocherfa230442006-12-21 17:17:02 +0100247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
249 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
Heiko Schocherfa230442006-12-21 17:17:02 +0100250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
252 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
Heiko Schocherfa230442006-12-21 17:17:02 +0100253#endif
254
255#define MIIDELAY udelay(1)
256
257
Heiko Schocherfa230442006-12-21 17:17:02 +0100258/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
259#define CONFIG_8260_CLKIN 66666666 /* in Hz */
260
261#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Heiko Schocherfa230442006-12-21 17:17:02 +0100263
264#undef CONFIG_WATCHDOG /* watchdog disabled */
265
266#define CONFIG_TIMESTAMP /* Print image info with timestamp */
267
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500268/*
269 * BOOTP options
270 */
271#define CONFIG_BOOTP_SUBNETMASK
272#define CONFIG_BOOTP_GATEWAY
273#define CONFIG_BOOTP_HOSTNAME
274#define CONFIG_BOOTP_BOOTPATH
275#define CONFIG_BOOTP_BOOTFILESIZE
Heiko Schocherfa230442006-12-21 17:17:02 +0100276
Heiko Schocherfa230442006-12-21 17:17:02 +0100277
Jon Loeliger26946902007-07-04 22:30:50 -0500278/*
279 * Command line configuration.
280 */
281#include <config_cmd_default.h>
282
283#define CONFIG_CMD_I2C
284#define CONFIG_CMD_DHCP
285#define CONFIG_CMD_MII
286#define CONFIG_CMD_NAND
287#define CONFIG_CMD_NFS
288#define CONFIG_CMD_PCI
289#define CONFIG_CMD_PING
290#define CONFIG_CMD_SNTP
291
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500292#if CONFIG_I2C
293 #define CONFIG_CMD_I2C
294 #define CONFIG_CMD_DATE
295 #define CONFIG_CMD_DTT
296 #define CONFIG_CMD_EEPROM
297#endif
298
Heiko Schocherfa230442006-12-21 17:17:02 +0100299
300/*
301 * Miscellaneous configurable options
302 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_LONGHELP /* undef to save memory */
304#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Heiko Schocherfa230442006-12-21 17:17:02 +0100305
306#if 0
307#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
309#ifdef CONFIG_SYS_HUSH_PARSER
310#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Heiko Schocherfa230442006-12-21 17:17:02 +0100311#endif
312#endif
313
Jon Loeliger26946902007-07-04 22:30:50 -0500314#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Heiko Schocherfa230442006-12-21 17:17:02 +0100316#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schocherfa230442006-12-21 17:17:02 +0100318#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
320#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
321#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocherfa230442006-12-21 17:17:02 +0100322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
324#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Heiko Schocherfa230442006-12-21 17:17:02 +0100325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
Heiko Schocherfa230442006-12-21 17:17:02 +0100327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Heiko Schocherfa230442006-12-21 17:17:02 +0100329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Heiko Schocherfa230442006-12-21 17:17:02 +0100331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */
Heiko Schocherfa230442006-12-21 17:17:02 +0100333
334/*
335 * For booting Linux, the board info and command line data
336 * have to be in the first 8 MB of memory, since this is
337 * the maximum mapped by the Linux kernel during initialization.
338 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocherfa230442006-12-21 17:17:02 +0100340
341/*-----------------------------------------------------------------------
342 * CAN stuff
343 *-----------------------------------------------------------------------
344 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_CAN_BASE 0x51000000
346#define CONFIG_SYS_CAN_SIZE 1
347#define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100348 BRx_PS_8 |\
349 BRx_MS_UPMC |\
350 BRx_V)
351
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100353 ORxU_BI)
354
355
356/* What should the base address of the main FLASH be and how big is
357 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
358 * The main FLASH is whichever is connected to *CS0.
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_FLASH0_BASE 0x40000000
361#define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */
Heiko Schocherfa230442006-12-21 17:17:02 +0100362
363/* Flash bank size (for preliminary settings)
364 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
Heiko Schocherfa230442006-12-21 17:17:02 +0100366
367/*-----------------------------------------------------------------------
368 * FLASH organization
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
371#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
Heiko Schocherfa230442006-12-21 17:17:02 +0100372
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200374#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
376#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
Heiko Schocherfa230442006-12-21 17:17:02 +0100377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
379#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Heiko Schocherfa230442006-12-21 17:17:02 +0100380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_UPDATE_FLASH_SIZE
Heiko Schocherfa230442006-12-21 17:17:02 +0100382
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200383#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200385#define CONFIG_ENV_SIZE 0x20000
386#define CONFIG_ENV_SECT_SIZE 0x20000
387#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
388#define CONFIG_ENV_SIZE_REDUND 0x20000
Heiko Schocherfa230442006-12-21 17:17:02 +0100389
390/* Where is the Hardwareinformation Block (from Monitor Sources) */
391#define MON_RES_LENGTH (0x0003FC00)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
Heiko Schocherfa230442006-12-21 17:17:02 +0100393#define HWIB_INFO_LEN 512
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
Heiko Schocherfa230442006-12-21 17:17:02 +0100395#define CIB_INFO_LEN 512
396
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */
398#define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */
399#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Heiko Schocherfa230442006-12-21 17:17:02 +0100400
401/*-----------------------------------------------------------------------
402 * NAND-FLASH stuff
403 *-----------------------------------------------------------------------
404 */
Jon Loeliger26946902007-07-04 22:30:50 -0500405#if defined(CONFIG_CMD_NAND)
Heiko Schocherfa230442006-12-21 17:17:02 +0100406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_NAND_CS_DIST 0x80
408#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20
409#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40
Heiko Schocherfa230442006-12-21 17:17:02 +0100410
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100412 BRx_PS_8 |\
413 BRx_MS_UPMB |\
414 BRx_V)
415
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100417 ORxU_BI |\
418 ORxU_EHTR_8IDLE)
419
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_NAND_SIZE 1
421#define CONFIG_SYS_NAND0_BASE 0x50000000
422#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
423#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
424#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
Heiko Schocherfa230442006-12-21 17:17:02 +0100425
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */
Heiko Schocherfa230442006-12-21 17:17:02 +0100427
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
429 CONFIG_SYS_NAND1_BASE, \
430 CONFIG_SYS_NAND2_BASE, \
431 CONFIG_SYS_NAND3_BASE, \
Heiko Schocherfa230442006-12-21 17:17:02 +0100432 }
433
434#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
435#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
436#define WRITE_NAND_UPM(d, adr, off) do \
437{ \
438 volatile unsigned char *addr = (unsigned char *) (adr + off); \
439 WRITE_NAND(d, addr); \
440} while(0)
441
Wolfgang Denk170c1972009-07-18 15:32:10 +0200442#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
443
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500444#endif /* CONFIG_CMD_NAND */
Heiko Schocherfa230442006-12-21 17:17:02 +0100445
446#define CONFIG_PCI
447#ifdef CONFIG_PCI
448#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
449#define CONFIG_PCI_PNP
450#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100452#define CONFIG_PCI_SCAN_SHOW
453#endif
454
455/*-----------------------------------------------------------------------
456 * Hard Reset Configuration Words
457 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
Heiko Schocherfa230442006-12-21 17:17:02 +0100459 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
Heiko Schocherfa230442006-12-21 17:17:02 +0100461 */
462#if 0
463#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
464
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
Heiko Schocherfa230442006-12-21 17:17:02 +0100466#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
Heiko Schocherfa230442006-12-21 17:17:02 +0100468#endif
469
470/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_HRCW_SLAVE1 0
472#define CONFIG_SYS_HRCW_SLAVE2 0
473#define CONFIG_SYS_HRCW_SLAVE3 0
474#define CONFIG_SYS_HRCW_SLAVE4 0
475#define CONFIG_SYS_HRCW_SLAVE5 0
476#define CONFIG_SYS_HRCW_SLAVE6 0
477#define CONFIG_SYS_HRCW_SLAVE7 0
Heiko Schocherfa230442006-12-21 17:17:02 +0100478
479/*-----------------------------------------------------------------------
480 * Internal Memory Mapped Register
481 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_IMMR 0xFFF00000
Heiko Schocherfa230442006-12-21 17:17:02 +0100483
484/*-----------------------------------------------------------------------
485 * Definitions for initial stack pointer and data area (in DPRAM)
486 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
488#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
489#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
490#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
491#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocherfa230442006-12-21 17:17:02 +0100492
493/*-----------------------------------------------------------------------
494 * Start addresses for the final memory configuration
495 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Heiko Schocherfa230442006-12-21 17:17:02 +0100497 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#define CONFIG_SYS_SDRAM_BASE 0x00000000
499#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
500#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
501#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
502#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
Heiko Schocherfa230442006-12-21 17:17:02 +0100503
504/*
505 * Internal Definitions
506 *
507 * Boot Flags
508 */
509#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
510#define BOOTFLAG_WARM 0x02 /* Software reboot */
511
Heiko Schocherfa230442006-12-21 17:17:02 +0100512/*-----------------------------------------------------------------------
513 * Cache Configuration
514 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger26946902007-07-04 22:30:50 -0500516#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200517# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Heiko Schocherfa230442006-12-21 17:17:02 +0100518#endif
519
520/*-----------------------------------------------------------------------
521 * HIDx - Hardware Implementation-dependent Registers 2-11
522 *-----------------------------------------------------------------------
523 * HID0 also contains cache control - initially enable both caches and
524 * invalidate contents, then the final state leaves only the instruction
525 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
526 * but Soft reset does not.
527 *
528 * HID1 has only read-only information - nothing to set.
529 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
Heiko Schocherfa230442006-12-21 17:17:02 +0100531 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
533#define CONFIG_SYS_HID2 0
Heiko Schocherfa230442006-12-21 17:17:02 +0100534
535/*-----------------------------------------------------------------------
536 * RMR - Reset Mode Register 5-5
537 *-----------------------------------------------------------------------
538 * turn on Checkstop Reset Enable
539 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_RMR RMR_CSRE
Heiko Schocherfa230442006-12-21 17:17:02 +0100541
542/*-----------------------------------------------------------------------
543 * BCR - Bus Configuration 4-25
544 *-----------------------------------------------------------------------
545 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546#define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */
Heiko Schocherfa230442006-12-21 17:17:02 +0100547#define BCR_APD01 0x10000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200548#define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */
Heiko Schocherfa230442006-12-21 17:17:02 +0100549
550/*-----------------------------------------------------------------------
551 * SIUMCR - SIU Module Configuration 4-31
552 *-----------------------------------------------------------------------
553 */
554#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00)
556#define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE)
Heiko Schocherfa230442006-12-21 17:17:02 +0100557#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00)
Heiko Schocherfa230442006-12-21 17:17:02 +0100559#endif
560
561/*-----------------------------------------------------------------------
562 * SYPCR - System Protection Control 4-35
563 * SYPCR can only be written once after reset!
564 *-----------------------------------------------------------------------
565 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
566 */
567#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200568#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
Heiko Schocherfa230442006-12-21 17:17:02 +0100569 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
570#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200571#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
Heiko Schocherfa230442006-12-21 17:17:02 +0100572 SYPCR_SWRI|SYPCR_SWP)
573#endif /* CONFIG_WATCHDOG */
574
575/*-----------------------------------------------------------------------
576 * TMCNTSC - Time Counter Status and Control 4-40
577 *-----------------------------------------------------------------------
578 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
579 * and enable Time Counter
580 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200581#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
Heiko Schocherfa230442006-12-21 17:17:02 +0100582
583/*-----------------------------------------------------------------------
584 * PISCR - Periodic Interrupt Status and Control 4-42
585 *-----------------------------------------------------------------------
586 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
587 * Periodic timer
588 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200589#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
Heiko Schocherfa230442006-12-21 17:17:02 +0100590
591/*-----------------------------------------------------------------------
592 * SCCR - System Clock Control 9-8
593 *-----------------------------------------------------------------------
594 * Ensure DFBRG is Divide by 16
595 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596#define CONFIG_SYS_SCCR SCCR_DFBRG01
Heiko Schocherfa230442006-12-21 17:17:02 +0100597
598/*-----------------------------------------------------------------------
599 * RCCR - RISC Controller Configuration 13-7
600 *-----------------------------------------------------------------------
601 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602#define CONFIG_SYS_RCCR 0
Heiko Schocherfa230442006-12-21 17:17:02 +0100603
604/*
605 * Init Memory Controller:
606 *
607 * Bank Bus Machine PortSz Device
608 * ---- --- ------- ------ ------
609 * 0 60x GPCM 32 bit FLASH
610 * 1 60x SDRAM 64 bit SDRAM
611 * 2 60x UPMB 8 bit NAND
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +0100612 * 3 60x UPMC 8 bit CAN
Heiko Schocherfa230442006-12-21 17:17:02 +0100613 *
614 */
615
616/* Initialize SDRAM
617 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618#undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */
Heiko Schocherfa230442006-12-21 17:17:02 +0100619
620#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */
621
622/* Minimum mask to separate preliminary
623 * address ranges for CS[0:2]
624 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200625#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
Heiko Schocherfa230442006-12-21 17:17:02 +0100626
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200627#define CONFIG_SYS_MPTPR 0x4000
Heiko Schocherfa230442006-12-21 17:17:02 +0100628
629/*-----------------------------------------------------------------------------
630 * Address for Mode Register Set (MRS) command
631 *-----------------------------------------------------------------------------
632 * In fact, the address is rather configuration data presented to the SDRAM on
633 * its address lines. Because the address lines may be mux'ed externally either
634 * for 8 column or 9 column devices, some bits appear twice in the 8260's
635 * address:
636 *
637 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
638 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
639 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
640 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
641 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
642 *-----------------------------------------------------------------------------
643 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200644#define CONFIG_SYS_MRS_OFFS 0x00000110
Heiko Schocherfa230442006-12-21 17:17:02 +0100645
Heiko Schocherfa230442006-12-21 17:17:02 +0100646/* Bank 0 - FLASH
647 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200648#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100649 BRx_PS_32 |\
650 BRx_MS_GPCM_P |\
651 BRx_V)
652
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200653#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100654 ORxG_CSNT |\
655 ORxG_ACS_DIV4 |\
656 ORxG_SCY_8_CLK |\
657 ORxG_TRLX)
658
659/* SDRAM on TQM8272 can have either 8 or 9 columns.
660 * The number affects configuration values.
661 */
662
663/* Bank 1 - 60x bus SDRAM
664 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200665#define CONFIG_SYS_PSRT 0x20 /* Low Value */
666/* #define CONFIG_SYS_PSRT 0x10 Fast Value */
667#define CONFIG_SYS_LSRT 0x20 /* Local Bus */
668#ifndef CONFIG_SYS_RAMBOOT
669#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100670 BRx_PS_64 |\
671 BRx_MS_SDRAM_P |\
672 BRx_V)
673
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200674#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL
Heiko Schocherfa230442006-12-21 17:17:02 +0100675
676/* SDRAM initialization values for 8-column chips
677 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200678#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100679 ORxS_BPD_4 |\
680 ORxS_ROWST_PBI1_A7 |\
681 ORxS_NUMR_12)
682
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200683#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100684 PSDMR_SDAM_A15_IS_A5 |\
685 PSDMR_BSMA_A12_A14 |\
686 PSDMR_SDA10_PBI1_A8 |\
687 PSDMR_RFRC_7_CLK |\
688 PSDMR_PRETOACT_2W |\
689 PSDMR_ACTTORW_2W |\
690 PSDMR_LDOTOPRE_1C |\
691 PSDMR_WRC_2C |\
692 PSDMR_EAMUX |\
693 PSDMR_BUFCMD |\
694 PSDMR_CL_2)
695
696
697/* SDRAM initialization values for 9-column chips
698 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200699#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100700 ORxS_BPD_4 |\
701 ORxS_ROWST_PBI1_A5 |\
702 ORxS_NUMR_13)
703
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200704#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100705 PSDMR_SDAM_A16_IS_A5 |\
706 PSDMR_BSMA_A12_A14 |\
707 PSDMR_SDA10_PBI1_A7 |\
708 PSDMR_RFRC_7_CLK |\
709 PSDMR_PRETOACT_2W |\
710 PSDMR_ACTTORW_2W |\
711 PSDMR_LDOTOPRE_1C |\
712 PSDMR_WRC_2C |\
713 PSDMR_EAMUX |\
714 PSDMR_BUFCMD |\
715 PSDMR_CL_2)
716
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200717#define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100718 ORxS_BPD_4 |\
719 ORxS_ROWST_PBI1_A4 |\
720 ORxS_NUMR_13)
721
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200722#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100723 PSDMR_SDAM_A17_IS_A5 |\
724 PSDMR_BSMA_A12_A14 |\
725 PSDMR_SDA10_PBI1_A4 |\
726 PSDMR_RFRC_6_CLK |\
727 PSDMR_PRETOACT_2W |\
728 PSDMR_ACTTORW_2W |\
729 PSDMR_LDOTOPRE_1C |\
730 PSDMR_WRC_2C |\
731 PSDMR_EAMUX |\
732 PSDMR_BUFCMD |\
733 PSDMR_CL_2)
734
Heiko Schocherfa230442006-12-21 17:17:02 +0100735#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
736#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */
737#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */
738#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */
739#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */
740#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */
741
742#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */
743#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */
744#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */
745#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */
746#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */
747#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */
748
749#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */
750#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */
751#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */
752#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */
753#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */
754#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */
755
756#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */
757#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */
758#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */
759#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */
760#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */
761#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */
762
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200763#endif /* CONFIG_SYS_RAMBOOT */
Heiko Schocherfa230442006-12-21 17:17:02 +0100764
765#endif /* __CONFIG_H */