blob: f896cb07a1752df2193a9c9fe691f313cbb46cce [file] [log] [blame]
Aubrey.Li3f0606a2007-03-09 13:38:44 +08001/*
2 * U-boot - Configuration file for BF533 EZKIT board
3 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF533_EZKIT_H__
6#define __CONFIG_BF533_EZKIT_H__
Aubrey.Li3f0606a2007-03-09 13:38:44 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Aubrey.Li3f0606a2007-03-09 13:38:44 +080010
Mike Frysingercf6f4692008-06-01 09:09:48 -040011/*
12 * Processor Settings
13 */
14#define CONFIG_BFIN_CPU bf533-0.3
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
Aubrey.Li3f0606a2007-03-09 13:38:44 +080016
Aubrey.Li3f0606a2007-03-09 13:38:44 +080017
Mike Frysingercf6f4692008-06-01 09:09:48 -040018/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 27000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 22
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 5
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_SIZE 32
46/* Early EZKITs had 32megs, but later have 64megs */
47#if (CONFIG_MEM_SIZE == 64)
48# define CONFIG_MEM_ADD_WDTH 10
49#else
50# define CONFIG_MEM_ADD_WDTH 9
51#endif
52
53#define CONFIG_EBIU_SDRRC_VAL 0x398
54#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
55
56#define CONFIG_EBIU_AMGCTL_VAL 0xFF
57#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
58#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
59
60#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
61#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
62
63
64/*
65 * Network Settings
66 */
67#define ADI_CMDS_NETWORK 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +080068#define CONFIG_DRIVER_SMC91111 1
69#define CONFIG_SMC91111_BASE 0x20310300
Mike Frysingercf6f4692008-06-01 09:09:48 -040070#define SMC91111_EEPROM_INIT() \
71 do { \
72 *pFIO_DIR |= PF1; \
73 *pFIO_FLAG_S = PF1; \
74 SSYNC(); \
75 } while (0)
76#define CONFIG_HOSTNAME bf533-ezkit
77/* Uncomment next line to use fixed MAC address */
78/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
Aubrey.Li3f0606a2007-03-09 13:38:44 +080079
80
Jon Loeligerba2351f2007-07-04 22:31:49 -050081/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040082 * Flash Settings
Jon Loeliger079a1362007-07-10 10:12:10 -050083 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040085#define CONFIG_SYS_MAX_FLASH_BANKS 3
86#define CONFIG_SYS_MAX_FLASH_SECT 40
87#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020088#define CONFIG_ENV_ADDR 0x20020000
Mike Frysingercf6f4692008-06-01 09:09:48 -040089#define CONFIG_ENV_SECT_SIZE 0x10000
Aubrey.Li3f0606a2007-03-09 13:38:44 +080090#define FLASH_TOT_SECT 40
Mike Frysingercf6f4692008-06-01 09:09:48 -040091
Aubrey.Li3f0606a2007-03-09 13:38:44 +080092
93/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040094 * I2C Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080095 * By default PF1 is used as SDA and PF0 as SCL on the Stamp board
96 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040097#define CONFIG_SOFT_I2C
98#ifdef CONFIG_SOFT_I2C
99#define PF_SCL PF0
100#define PF_SDA PF1
101#define I2C_INIT \
102 do { \
103 *pFIO_DIR |= PF_SCL; \
104 SSYNC(); \
105 } while (0)
106#define I2C_ACTIVE \
107 do { \
108 *pFIO_DIR |= PF_SDA; \
109 *pFIO_INEN &= ~PF_SDA; \
110 SSYNC(); \
111 } while (0)
112#define I2C_TRISTATE \
113 do { \
114 *pFIO_DIR &= ~PF_SDA; \
115 *pFIO_INEN |= PF_SDA; \
116 SSYNC(); \
117 } while (0)
118#define I2C_READ ((*pFIO_FLAG_D & PF_SDA) != 0)
119#define I2C_SDA(bit) \
120 do { \
121 if (bit) \
122 *pFIO_FLAG_S = PF_SDA; \
123 else \
124 *pFIO_FLAG_C = PF_SDA; \
125 SSYNC(); \
126 } while (0)
127#define I2C_SCL(bit) \
128 do { \
129 if (bit) \
130 *pFIO_FLAG_S = PF_SCL; \
131 else \
132 *pFIO_FLAG_C = PF_SCL; \
133 SSYNC(); \
134 } while (0)
135#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_I2C_SPEED 50000
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400138#define CONFIG_SYS_I2C_SLAVE 0
Mike Frysingercf6f4692008-06-01 09:09:48 -0400139#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800140
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800141
Mike Frysingercf6f4692008-06-01 09:09:48 -0400142/*
143 * Misc Settings
144 */
145#define CONFIG_MISC_INIT_R
146#define CONFIG_RTC_BFIN
147#define CONFIG_UART_CONSOLE 0
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800148
Mike Frysingercf6f4692008-06-01 09:09:48 -0400149
150/*
151 * Pull in common ADI header for remaining command/environment setup
152 */
153#include <configs/bfin_adi_common.h>
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800154
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800155#endif