stroese | a65cb68 | 2003-09-12 08:41:39 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001-2003 |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <asm/processor.h> |
| 26 | #include <command.h> |
| 27 | #include <malloc.h> |
| 28 | |
| 29 | /* ------------------------------------------------------------------------- */ |
| 30 | |
| 31 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame^] | 32 | int board_early_init_f (void) |
stroese | a65cb68 | 2003-09-12 08:41:39 +0000 | [diff] [blame] | 33 | { |
| 34 | /* |
| 35 | * IRQ 0-15 405GP internally generated; active high; level sensitive |
| 36 | * IRQ 16 405GP internally generated; active low; level sensitive |
| 37 | * IRQ 17-24 RESERVED |
| 38 | * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive |
| 39 | * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive |
| 40 | * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive |
| 41 | * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive |
| 42 | * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive |
| 43 | * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive |
| 44 | * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive |
| 45 | */ |
| 46 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
| 47 | mtdcr(uicer, 0x00000000); /* disable all ints */ |
| 48 | mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ |
| 49 | mtdcr(uicpr, 0xFFFFFF9F); /* set int polarities */ |
| 50 | mtdcr(uictr, 0x10000000); /* set int trigger levels */ |
| 51 | mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ |
| 52 | mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ |
| 53 | |
| 54 | /* |
| 55 | * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us |
| 56 | */ |
| 57 | mtebc (epcr, 0xa8400000); /* ebc always driven */ |
| 58 | |
| 59 | return 0; |
| 60 | } |
| 61 | |
| 62 | |
| 63 | /* ------------------------------------------------------------------------- */ |
| 64 | |
| 65 | int misc_init_f (void) |
| 66 | { |
| 67 | return 0; /* dummy implementation */ |
| 68 | } |
| 69 | |
| 70 | |
| 71 | int misc_init_r (void) |
| 72 | { |
| 73 | volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4); |
| 74 | volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4); |
| 75 | volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4); |
| 76 | volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4); |
| 77 | |
| 78 | /* |
| 79 | * Reset external DUARTs |
| 80 | */ |
| 81 | out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */ |
| 82 | udelay(10); /* wait 10us */ |
| 83 | out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */ |
| 84 | udelay(1000); /* wait 1ms */ |
| 85 | |
| 86 | /* |
| 87 | * Enable interrupts in exar duart mcr[3] |
| 88 | */ |
| 89 | *duart0_mcr = 0x08; |
| 90 | *duart1_mcr = 0x08; |
| 91 | *duart2_mcr = 0x08; |
| 92 | *duart3_mcr = 0x08; |
| 93 | |
| 94 | /* |
| 95 | * Set NAND-FLASH GPIO signals to default |
| 96 | */ |
| 97 | out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE)); |
| 98 | out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE); |
| 99 | |
| 100 | return (0); |
| 101 | } |
| 102 | |
| 103 | |
| 104 | /* |
| 105 | * Check Board Identity: |
| 106 | */ |
| 107 | |
| 108 | int checkboard (void) |
| 109 | { |
| 110 | unsigned char str[64]; |
| 111 | int i = getenv_r ("serial#", str, sizeof(str)); |
| 112 | |
| 113 | puts ("Board: "); |
| 114 | |
| 115 | if (i == -1) { |
| 116 | puts ("### No HW ID - assuming HUB405"); |
| 117 | } else { |
| 118 | puts(str); |
| 119 | } |
| 120 | |
| 121 | putc ('\n'); |
| 122 | |
| 123 | return 0; |
| 124 | } |
| 125 | |
| 126 | /* ------------------------------------------------------------------------- */ |
| 127 | |
| 128 | long int initdram (int board_type) |
| 129 | { |
| 130 | unsigned long val; |
| 131 | |
| 132 | mtdcr(memcfga, mem_mb0cf); |
| 133 | val = mfdcr(memcfgd); |
| 134 | |
| 135 | #if 0 |
| 136 | printf("\nmb0cf=%x\n", val); /* test-only */ |
| 137 | printf("strap=%x\n", mfdcr(strap)); /* test-only */ |
| 138 | #endif |
| 139 | |
| 140 | return (4*1024*1024 << ((val & 0x000e0000) >> 17)); |
| 141 | } |
| 142 | |
| 143 | /* ------------------------------------------------------------------------- */ |
| 144 | |
| 145 | int testdram (void) |
| 146 | { |
| 147 | /* TODO: XXX XXX XXX */ |
| 148 | printf ("test: 16 MB - ok\n"); |
| 149 | |
| 150 | return (0); |
| 151 | } |
| 152 | |
| 153 | /* ------------------------------------------------------------------------- */ |
| 154 | |
| 155 | #if (CONFIG_COMMANDS & CFG_CMD_NAND) |
| 156 | #include <linux/mtd/nand.h> |
| 157 | extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; |
| 158 | |
| 159 | void nand_init(void) |
| 160 | { |
| 161 | nand_probe(CFG_NAND_BASE); |
| 162 | if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { |
| 163 | print_size(nand_dev_desc[0].totlen, "\n"); |
| 164 | } |
| 165 | } |
| 166 | #endif |