| wdenk | acea76a | 2002-09-20 09:17:33 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /************************************************************************ |
| 24 | * board/config_EBONY.h - configuration for IBM 440GP Ref (Ebony) |
| 25 | ***********************************************************************/ |
| 26 | |
| 27 | #ifndef __CONFIG_H |
| 28 | #define __CONFIG_H |
| 29 | |
| 30 | /*----------------------------------------------------------------------- |
| 31 | * High Level Configuration Options |
| 32 | *----------------------------------------------------------------------*/ |
| 33 | #define CONFIG_EBONY 1 /* Board is ebony */ |
| 34 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
| wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame^] | 35 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| wdenk | acea76a | 2002-09-20 09:17:33 +0000 | [diff] [blame] | 36 | #undef CFG_DRAM_TEST /* Disable-takes long time! */ |
| 37 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
| 38 | |
| 39 | /*----------------------------------------------------------------------- |
| 40 | * Base addresses -- Note these are effective addresses where the |
| 41 | * actual resources get mapped (not physical addresses) |
| 42 | *----------------------------------------------------------------------*/ |
| 43 | #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ |
| 44 | #define CFG_FLASH_BASE 0xff800000 /* start of FLASH */ |
| 45 | #define CFG_MONITOR_BASE 0xfff80000 /* start of monitor */ |
| 46 | #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ |
| 47 | #define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ |
| 48 | #define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ |
| 49 | #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ |
| 50 | |
| 51 | #define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) |
| 52 | #define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) |
| 53 | |
| 54 | /*----------------------------------------------------------------------- |
| 55 | * Initial RAM & stack pointer (placed in internal SRAM) |
| 56 | *----------------------------------------------------------------------*/ |
| 57 | #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ |
| 58 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
| 59 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 60 | |
| 61 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 62 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 63 | |
| 64 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 65 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ |
| 66 | |
| 67 | /*----------------------------------------------------------------------- |
| 68 | * Serial Port |
| 69 | *----------------------------------------------------------------------*/ |
| 70 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 71 | #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ |
| 72 | #define CONFIG_BAUDRATE 9600 |
| 73 | |
| 74 | #define CFG_BAUDRATE_TABLE \ |
| 75 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} |
| 76 | |
| 77 | /*----------------------------------------------------------------------- |
| 78 | * NVRAM/RTC |
| 79 | * |
| 80 | * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located. |
| 81 | * The DS1743 code assumes this condition (i.e. -- it assumes the base |
| 82 | * address for the RTC registers is: |
| 83 | * |
| 84 | * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE |
| 85 | * |
| 86 | *----------------------------------------------------------------------*/ |
| 87 | #define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */ |
| 88 | #define CONFIG_RTC_DS174x 1 /* DS1743 RTC */ |
| 89 | |
| 90 | /*----------------------------------------------------------------------- |
| 91 | * FLASH related |
| 92 | *----------------------------------------------------------------------*/ |
| 93 | #define CFG_MAX_FLASH_BANKS 3 /* number of banks */ |
| 94 | #define CFG_MAX_FLASH_SECT 32 /* sectors per device */ |
| 95 | |
| 96 | #undef CFG_FLASH_CHECKSUM |
| 97 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 98 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
| 99 | |
| 100 | /*----------------------------------------------------------------------- |
| 101 | * DDR SDRAM |
| 102 | *----------------------------------------------------------------------*/ |
| 103 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ |
| 104 | #define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ |
| 105 | |
| 106 | /*----------------------------------------------------------------------- |
| 107 | * I2C |
| 108 | *----------------------------------------------------------------------*/ |
| 109 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ |
| 110 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 111 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 112 | #define CFG_I2C_SLAVE 0x7F |
| 113 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
| 114 | |
| 115 | |
| 116 | /*----------------------------------------------------------------------- |
| 117 | * Environment |
| 118 | *----------------------------------------------------------------------*/ |
| 119 | #define CFG_ENV_IS_IN_NVRAM 1 /* Environment uses NVRAM */ |
| 120 | #undef CFG_ENV_IS_IN_FLASH /* ... not in flash */ |
| 121 | #undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ |
| 122 | |
| 123 | #define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
| 124 | #define CFG_ENV_ADDR \ |
| 125 | (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) |
| 126 | |
| 127 | #define CONFIG_BOOTARGS "root=/dev/hda1 " |
| 128 | #define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ |
| 129 | #define CONFIG_BOOTDELAY -1 /* disable autoboot */ |
| 130 | #define CONFIG_BAUDRATE 9600 |
| 131 | |
| 132 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 133 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 134 | |
| 135 | #define CONFIG_MII 1 /* MII PHY management */ |
| 136 | #define CONFIG_PHY_ADDR 8 /* PHY address */ |
| 137 | |
| 138 | |
| 139 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
| 140 | CFG_CMD_PCI | \ |
| 141 | CFG_CMD_IRQ | \ |
| 142 | CFG_CMD_I2C | \ |
| 143 | CFG_CMD_KGDB | \ |
| 144 | CFG_CMD_DHCP | \ |
| 145 | CFG_CMD_DATE | \ |
| 146 | CFG_CMD_BEDBUG | \ |
| 147 | CFG_CMD_ELF ) |
| 148 | |
| 149 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
| 150 | #include <cmd_confdefs.h> |
| 151 | |
| 152 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 153 | |
| 154 | /* |
| 155 | * Miscellaneous configurable options |
| 156 | */ |
| 157 | #define CFG_LONGHELP /* undef to save memory */ |
| 158 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 159 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 160 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 161 | #else |
| 162 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 163 | #endif |
| 164 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 165 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 166 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 167 | |
| 168 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
| 169 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
| 170 | |
| 171 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
| 172 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
| 173 | |
| 174 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 175 | |
| 176 | |
| 177 | /*----------------------------------------------------------------------- |
| 178 | * PCI stuff |
| 179 | *----------------------------------------------------------------------- |
| 180 | */ |
| 181 | /* General PCI */ |
| 182 | #define CONFIG_PCI /* include pci support */ |
| 183 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 184 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 185 | #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ |
| 186 | |
| 187 | /* Board-specific PCI */ |
| 188 | #define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ |
| 189 | #define CFG_PCI_TARGET_INIT /* let board init pci target */ |
| 190 | |
| 191 | #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ |
| 192 | #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
| 193 | |
| 194 | /* |
| 195 | * For booting Linux, the board info and command line data |
| 196 | * have to be in the first 8 MB of memory, since this is |
| 197 | * the maximum mapped by the Linux kernel during initialization. |
| 198 | */ |
| 199 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 200 | /*----------------------------------------------------------------------- |
| 201 | * Cache Configuration |
| 202 | */ |
| 203 | #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */ |
| 204 | #define CFG_CACHELINE_SIZE 32 /* ... */ |
| 205 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 206 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 207 | #endif |
| 208 | |
| 209 | /* |
| 210 | * Internal Definitions |
| 211 | * |
| 212 | * Boot Flags |
| 213 | */ |
| 214 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 215 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 216 | |
| 217 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 218 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 219 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 220 | #endif |
| 221 | #endif /* __CONFIG_H */ |