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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/***********************************************************
32 * High Level Configuration Options
33 * (easy to change)
34 ***********************************************************/
35#define CONFIG_405GP 1 /* This is a PPC405 CPU */
36#define CONFIG_4xx 1 /* ...member of PPC4xx family */
37#define CONFIG_PIP405 1 /* ...on a PIP405 board */
38/***********************************************************
39 * Clock
40 ***********************************************************/
41#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
42
43/***********************************************************
44 * Command definitions
45 ***********************************************************/
46#define CONFIG_COMMANDS \
47 (CONFIG_CMD_DFL | \
48 CFG_CMD_IDE | \
49 CFG_CMD_DHCP | \
50 CFG_CMD_PCI | \
51 CFG_CMD_CACHE | \
52 CFG_CMD_IRQ | \
wdenk7205e402003-09-10 22:30:53 +000053 CFG_CMD_ECHO | \
wdenkc6097192002-11-03 00:24:07 +000054 CFG_CMD_EEPROM | \
55 CFG_CMD_I2C | \
56 CFG_CMD_REGINFO | \
57 CFG_CMD_FDC | \
58 CFG_CMD_SCSI | \
wdenk7205e402003-09-10 22:30:53 +000059 CFG_CMD_FAT | \
wdenkc6097192002-11-03 00:24:07 +000060 CFG_CMD_DATE | \
61 CFG_CMD_ELF | \
62 CFG_CMD_USB | \
63 CFG_CMD_MII | \
64 CFG_CMD_SDRAM | \
65 CFG_CMD_DOC | \
wdenk27b207f2003-07-24 23:38:38 +000066 CFG_CMD_PING | \
wdenkc6097192002-11-03 00:24:07 +000067 CFG_CMD_SAVES | \
68 CFG_CMD_BSP )
69/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
70#include <cmd_confdefs.h>
71
72#define CFG_HUSH_PARSER
73#define CFG_PROMPT_HUSH_PS2 "> "
74/**************************************************************
75 * I2C Stuff:
76 * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
77 * 0x53.
78 * Caution: on the same bus is the SPD (Serial Presens Detect
79 * EEPROM of the SDRAM
80 * The Atmel EEPROM uses 16Bit addressing.
81 ***************************************************************/
82#define CONFIG_HARD_I2C /* I2c with hardware support */
83#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
84#define CFG_I2C_SLAVE 0x7F
85
86#define CFG_I2C_EEPROM_ADDR 0x53
87#define CFG_I2C_EEPROM_ADDR_LEN 2
88#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
89#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
90#define CFG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
91
92#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
93#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
94 /* 64 byte page write mode using*/
95 /* last 6 bits of the address */
96#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
97#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
98
99
100/***************************************************************
101 * Definitions for Serial Presence Detect EEPROM address
102 * (to get SDRAM settings)
103 ***************************************************************/
104#define SPD_EEPROM_ADDRESS 0x50
105
wdenkc837dcb2004-01-20 23:12:12 +0000106#define CONFIG_BOARD_EARLY_INIT_F
wdenkc6097192002-11-03 00:24:07 +0000107/**************************************************************
108 * Environment definitions
109 **************************************************************/
110#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
111
112
113#define CONFIG_BOOTDELAY 5
114/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
115#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
116#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
117
118
wdenk3e386912003-04-05 00:53:31 +0000119#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
wdenkc6097192002-11-03 00:24:07 +0000120#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
121
122#define CONFIG_IPADDR 10.0.0.100
123#define CONFIG_SERVERIP 10.0.0.1
124#define CONFIG_PREBOOT
125/***************************************************************
126 * defines if the console is stored in the environment
127 ***************************************************************/
128#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
129/***************************************************************
130 * defines if an overwrite_console function exists
131 *************************************************************/
132#define CFG_CONSOLE_OVERWRITE_ROUTINE
133#define CFG_CONSOLE_INFO_QUIET
134/***************************************************************
135 * defines if the overwrite_console should be stored in the
136 * environment
137 **************************************************************/
138#undef CFG_CONSOLE_ENV_OVERWRITE
139
140/**************************************************************
141 * loads config
142 *************************************************************/
143#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
144#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
145
wdenk7205e402003-09-10 22:30:53 +0000146#define CONFIG_MISC_INIT_R
wdenkc6097192002-11-03 00:24:07 +0000147/***********************************************************
148 * Miscellaneous configurable options
149 **********************************************************/
150#define CFG_LONGHELP /* undef to save memory */
151#define CFG_PROMPT "=> " /* Monitor Command Prompt */
152#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
153#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
154#else
155#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
156#endif
157#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
158#define CFG_MAXARGS 16 /* max number of command args */
159#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
160
161#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
162#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
163
164#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
165#define CFG_BASE_BAUD 691200
166
167/* The following table includes the supported baudrates */
168#define CFG_BAUDRATE_TABLE \
169 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
170 57600, 115200, 230400, 460800, 921600 }
171
wdenk3e386912003-04-05 00:53:31 +0000172#define CFG_LOAD_ADDR 0x400000 /* default load address */
wdenkc6097192002-11-03 00:24:07 +0000173#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
174
175#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
176
177/*-----------------------------------------------------------------------
178 * PCI stuff
179 *-----------------------------------------------------------------------
180 */
181#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
182#define PCI_HOST_FORCE 1 /* configure as pci host */
183#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
184
185#define CONFIG_PCI /* include pci support */
186#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
187#define CONFIG_PCI_PNP /* pci plug-and-play */
188 /* resource configuration */
189#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
190#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
191#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
192#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
193#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
194#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
195#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
196#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
197
198/*-----------------------------------------------------------------------
199 * Start addresses for the final memory configuration
200 * (Set up by the startup code)
201 * Please note that CFG_SDRAM_BASE _must_ start at 0
202 */
203#define CFG_SDRAM_BASE 0x00000000
204#define CFG_FLASH_BASE 0xFFF80000
205#define CFG_MONITOR_BASE CFG_FLASH_BASE
206#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
wdenka2663ea2003-12-07 18:32:37 +0000207#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000208
209/*
210 * For booting Linux, the board info and command line data
211 * have to be in the first 8 MB of memory, since this is
212 * the maximum mapped by the Linux kernel during initialization.
213 */
214#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
215/*-----------------------------------------------------------------------
216 * FLASH organization
217 */
218#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
219#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
220
221#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
222#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
223
224/*-----------------------------------------------------------------------
225 * Cache Configuration
226 */
227#define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
228#define CFG_CACHELINE_SIZE 32 /* ... */
229#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
230#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
231#endif
232
233/*
234 * Init Memory Controller:
235 */
wdenk7205e402003-09-10 22:30:53 +0000236#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */
237#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */
238/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
239#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */
wdenkc6097192002-11-03 00:24:07 +0000240
wdenkc837dcb2004-01-20 23:12:12 +0000241#define CONFIG_BOARD_EARLY_INIT_F
wdenkc6097192002-11-03 00:24:07 +0000242
243/* Configuration Port location */
244#define CONFIG_PORT_ADDR 0xF4000000
245#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
246
247
wdenkc6097192002-11-03 00:24:07 +0000248/*-----------------------------------------------------------------------
249 * Definitions for initial stack pointer and data area (in On Chip SRAM)
250 */
251#define CFG_TEMP_STACK_OCM 1
252#define CFG_OCM_DATA_ADDR 0xF0000000
253#define CFG_OCM_DATA_SIZE 0x1000
254#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
255#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
256#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
257#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
258#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
259
260/*
261 * Internal Definitions
262 *
263 * Boot Flags
264 */
265#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
266#define BOOTFLAG_WARM 0x02 /* Software reboot */
267
268
269/***********************************************************************
270 * External peripheral base address
271 ***********************************************************************/
272#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
273
274/***********************************************************************
275 * Last Stage Init
276 ***********************************************************************/
277#define CONFIG_LAST_STAGE_INIT
278/************************************************************
279 * Ethernet Stuff
280 ***********************************************************/
281#define CONFIG_MII 1 /* MII PHY management */
282#define CONFIG_PHY_ADDR 1 /* PHY address */
283#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */
284/************************************************************
285 * RTC
286 ***********************************************************/
287#define CONFIG_RTC_MC146818
288#undef CONFIG_WATCHDOG /* watchdog disabled */
289
290/************************************************************
291 * IDE/ATA stuff
292 ************************************************************/
293#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
294#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
295
296#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
297#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
298#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
299#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
300#define CFG_ATA_REG_OFFSET 0 /* reg offset */
301#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
302
303#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
304#undef CONFIG_IDE_LED /* no led for ide supported */
305#define CONFIG_IDE_RESET /* reset for ide supported... */
306#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
wdenk7205e402003-09-10 22:30:53 +0000307#define CONFIG_SUPPORT_VFAT
wdenkc6097192002-11-03 00:24:07 +0000308
309/************************************************************
310 * ATAPI support (experimental)
311 ************************************************************/
312#define CONFIG_ATAPI /* enable ATAPI Support */
313
314/************************************************************
315 * SCSI support (experimental) only SYM53C8xx supported
316 ************************************************************/
317#define CONFIG_SCSI_SYM53C8XX
318#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
319#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
320#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
321#define CFG_SCSI_SPIN_UP_TIME 2
322
323/************************************************************
324 * Disk-On-Chip configuration
325 ************************************************************/
326#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
327#define CFG_DOC_SHORT_TIMEOUT
328#define CFG_DOC_SUPPORT_2000
329#define CFG_DOC_SUPPORT_MILLENNIUM
330
331/************************************************************
332 * DISK Partition support
333 ************************************************************/
334#define CONFIG_DOS_PARTITION
335#define CONFIG_MAC_PARTITION
336#define CONFIG_ISO_PARTITION /* Experimental */
337
338/************************************************************
339 * Keyboard support
340 ************************************************************/
341#define CONFIG_ISA_KEYBOARD
342
343/************************************************************
344 * Video support
345 ************************************************************/
346#define CONFIG_VIDEO /*To enable video controller support */
347#define CONFIG_VIDEO_CT69000
348#define CONFIG_CFB_CONSOLE
349#define CONFIG_VIDEO_LOGO
350#define CONFIG_CONSOLE_EXTRA_INFO
351#define CONFIG_VGA_AS_SINGLE_DEVICE
352#define CONFIG_VIDEO_SW_CURSOR
353#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
354
355/************************************************************
356 * USB support
357 ************************************************************/
358#define CONFIG_USB_UHCI
359#define CONFIG_USB_KEYBOARD
360#define CONFIG_USB_STORAGE
361
362/* Enable needed helper functions */
363#define CFG_DEVICE_DEREGISTER /* needs device_deregister */
364
365/************************************************************
366 * Debug support
367 ************************************************************/
368#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
369#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
370#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
371#endif
372
373/************************************************************
wdenka2663ea2003-12-07 18:32:37 +0000374 * support BZIP2 compression
375 ************************************************************/
376#define CONFIG_BZIP2 1
377
378/************************************************************
wdenkc6097192002-11-03 00:24:07 +0000379 * Ident
380 ************************************************************/
381#define VERSION_TAG "released"
wdenkf3e0de62003-06-04 15:05:30 +0000382#define CONFIG_ISO_STRING "MEV-10066-001"
383#define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
wdenkc6097192002-11-03 00:24:07 +0000384
385
386#endif /* __CONFIG_H */