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Haiying Wang765547d2009-03-27 17:02:45 -04001/*
2 * Copyright 2009 Freescale Semiconductor.
3 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <pci.h>
27#include <asm/processor.h>
28#include <asm/mmu.h>
29#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050030#include <asm/fsl_pci.h>
Haiying Wang765547d2009-03-27 17:02:45 -040031#include <asm/fsl_ddr_sdram.h>
32#include <asm/io.h>
33#include <spd_sdram.h>
34#include <i2c.h>
35#include <ioports.h>
36#include <libfdt.h>
37#include <fdt_support.h>
38
39#include "bcsr.h"
40
41phys_size_t fixed_sdram(void);
42
43const qe_iop_conf_t qe_iop_conf_tab[] = {
44 /* QE_MUX_MDC */
45 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
46
47 /* QE_MUX_MDIO */
48 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
49
50 /* UCC_1_RGMII */
51 {2, 11, 2, 0, 1}, /* CLK12 */
52 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
53 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
54 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
55 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
56 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
57 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
58 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
59 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
60 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
61 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
62 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
63 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
64
65 /* UCC_2_RGMII */
66 {2, 16, 2, 0, 3}, /* CLK17 */
67 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
68 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
69 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
70 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
71 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
72 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
73 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
74 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
75 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
76 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
77 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
78 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
79
80 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
81};
82
83void local_bus_init(void);
84
85int board_early_init_f (void)
86{
87 /*
88 * Initialize local bus.
89 */
90 local_bus_init ();
91
92 enable_8569mds_flash_write();
93
94#ifdef CONFIG_QE
95 enable_8569mds_qe_mdio();
96#endif
97
98#if CONFIG_SYS_I2C2_OFFSET
99 /* Enable I2C2 signals instead of SD signals */
100 volatile struct ccsr_gur *gur;
101 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
102 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
103 gur->plppar1 |= PLPPAR1_I2C2_VAL;
104 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
105 gur->plpdir1 |= PLPDIR1_I2C2_VAL;
106
107 disable_8569mds_brd_eeprom_write_protect();
108#endif
109
110 return 0;
111}
112
113int checkboard (void)
114{
115 printf ("Board: 8569 MDS\n");
116
117 return 0;
118}
119
120phys_size_t
121initdram(int board_type)
122{
123 long dram_size = 0;
124
125 puts("Initializing\n");
126
127#if defined(CONFIG_DDR_DLL)
128 /*
129 * Work around to stabilize DDR DLL MSYNC_IN.
130 * Errata DDR9 seems to have been fixed.
131 * This is now the workaround for Errata DDR11:
132 * Override DLL = 1, Course Adj = 1, Tap Select = 0
133 */
134 volatile ccsr_gur_t *gur =
135 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
136
137 out_be32(&gur->ddrdllcr, 0x81000000);
138 udelay(200);
139#endif
140
141#ifdef CONFIG_SPD_EEPROM
142 dram_size = fsl_ddr_sdram();
143#else
144 dram_size = fixed_sdram();
145#endif
146
147 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
148 dram_size *= 0x100000;
149
150 puts(" DDR: ");
151 return dram_size;
152}
153
154#if !defined(CONFIG_SPD_EEPROM)
155phys_size_t fixed_sdram(void)
156{
157 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
158 uint d_init;
159
160 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
161 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
162 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
163 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
164 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
165 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
166 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
167 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
168 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
169 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
170 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
171 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
172 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
173 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
174 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
175 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
176 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
177 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
178#if defined (CONFIG_DDR_ECC)
179 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
180 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
181 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
182#endif
183 udelay(500);
184
185 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
186#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
187 d_init = 1;
188 debug("DDR - 1st controller: memory initializing\n");
189 /*
190 * Poll until memory is initialized.
191 * 512 Meg at 400 might hit this 200 times or so.
192 */
193 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
194 udelay(1000);
195 }
196 debug("DDR: memory initialized\n\n");
197 udelay(500);
198#endif
199 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
200}
201#endif
202
203/*
204 * Initialize Local Bus
205 */
206void
207local_bus_init(void)
208{
209 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
210 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
211
212 uint clkdiv;
213 uint lbc_hz;
214 sys_info_t sysinfo;
215
216 get_sys_info(&sysinfo);
217 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
218 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
219
220 out_be32(&gur->lbiuiplldcr1, 0x00078080);
221 if (clkdiv == 16)
222 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
223 else if (clkdiv == 8)
224 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
225 else if (clkdiv == 4)
226 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
227
228 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
229}
230
231#ifdef CONFIG_PCIE1
232static struct pci_controller pcie1_hose;
233#endif /* CONFIG_PCIE1 */
234
235extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
236extern void fsl_pci_init(struct pci_controller *hose);
237
238int first_free_busno = 0;
239
240#ifdef CONFIG_PCI
241void
242pci_init_board(void)
243{
244 volatile ccsr_gur_t *gur;
245 uint io_sel;
246 uint host_agent;
247
248 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
249 io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
250 host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
251
252#ifdef CONFIG_PCIE1
253{
254 volatile ccsr_fsl_pci_t *pci;
255 struct pci_controller *hose;
256 int pcie_ep;
257 struct pci_region *r;
258 int pcie_configured;
259
260 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
261 hose = &pcie1_hose;
262 pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
263 r = hose->regions;
264 pcie_configured = io_sel >= 1;
265
266 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
267 printf ("\n PCIE connected to slot as %s (base address %x)",
268 pcie_ep ? "End Point" : "Root Complex",
269 (uint)pci);
270
271 if (pci->pme_msg_det) {
272 pci->pme_msg_det = 0xffffffff;
273 debug (" with errors. Clearing. Now 0x%08x",
274 pci->pme_msg_det);
275 }
276 printf ("\n");
277
278 /* inbound */
279 r += fsl_pci_setup_inbound_windows(r);
280
281 /* outbound memory */
282 pci_set_region(r++,
283 CONFIG_SYS_PCIE1_MEM_BUS,
284 CONFIG_SYS_PCIE1_MEM_PHYS,
285 CONFIG_SYS_PCIE1_MEM_SIZE,
286 PCI_REGION_MEM);
287
288 /* outbound io */
289 pci_set_region(r++,
290 CONFIG_SYS_PCIE1_IO_BUS,
291 CONFIG_SYS_PCIE1_IO_PHYS,
292 CONFIG_SYS_PCIE1_IO_SIZE,
293 PCI_REGION_IO);
294
295 hose->region_count = r - hose->regions;
296
297 hose->first_busno=first_free_busno;
298 pci_setup_indirect(hose, (int) &pci->cfg_addr,
299 (int) &pci->cfg_data);
300
301 fsl_pci_init(hose);
302 printf ("PCIE on bus %02x - %02x\n",
303 hose->first_busno,hose->last_busno);
304
305 first_free_busno=hose->last_busno+1;
306
307 } else {
308 printf (" PCIE: disabled\n");
309 }
310}
311#else
312 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
313#endif
314}
315#endif /* CONFIG_PCI */
316
317#if defined(CONFIG_OF_BOARD_SETUP)
318extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
319 struct pci_controller *hose);
320
321void ft_board_setup(void *blob, bd_t *bd)
322{
323 ft_cpu_setup(blob, bd);
324
325#ifdef CONFIG_PCIE1
326 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
327#endif
328}
329#endif