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wdenk9dd41a72005-05-12 22:48:09 +00001/*
2 * (C) Copyright 2005
3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37#define CONFIG_MPC8272_FAMILY 1
38#define CONFIG_IDS8247 1
39#define CPU_ID_STR "MPC8247"
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050040#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk9dd41a72005-05-12 22:48:09 +000041
42#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
43
44#define CONFIG_BOOTCOUNT_LIMIT
45
46#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
47
48#undef CONFIG_BOOTARGS
49
50#define CONFIG_EXTRA_ENV_SETTINGS \
51 "netdev=eth0\0" \
52 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010053 "nfsroot=${serverip}:${rootpath}\0" \
wdenk9dd41a72005-05-12 22:48:09 +000054 "ramargs=setenv bootargs root=/dev/ram rw " \
55 "console=ttyS0,115200\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010056 "addip=setenv bootargs ${bootargs} " \
57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
58 ":${hostname}:${netdev}:off panic=1\0" \
wdenk9dd41a72005-05-12 22:48:09 +000059 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "bootm ${kernel_addr}\0" \
wdenk9dd41a72005-05-12 22:48:09 +000061 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
63 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk9dd41a72005-05-12 22:48:09 +000064 "rootpath=/opt/eldk/ppc_82xx\0" \
65 "bootfile=/tftpboot/IDS8247/uImage\0" \
66 "kernel_addr=ff800000\0" \
67 "ramdisk_addr=ffa00000\0" \
68 ""
69#define CONFIG_BOOTCOMMAND "run flash_self"
70
71#define CONFIG_MISC_INIT_R 1
72
73/* enable I2C and select the hardware/software driver */
74#undef CONFIG_HARD_I2C /* I2C with hardware support */
75#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
76#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
77#define CFG_I2C_SLAVE 0x7F
78
79/*
80 * Software (bit-bang) I2C driver configuration
81 */
82
83#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */
84#define I2C_ACTIVE (iop->pdir |= 0x00000080)
85#define I2C_TRISTATE (iop->pdir &= ~0x00000080)
86#define I2C_READ ((iop->pdat & 0x00000080) != 0)
87#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \
88 else iop->pdat &= ~0x00000080
89#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \
90 else iop->pdat &= ~0x00000100
91#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
92
93#if 0
94#define CFG_I2C_EEPROM_ADDR 0x50
95#define CFG_I2C_EEPROM_ADDR_LEN 2
96#define CFG_EEPROM_PAGE_WRITE_BITS 4
97#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
98
99#define CONFIG_I2C_X
100#endif
101
102/*
103 * select serial console configuration
104 * use the extern UART for the console
105 */
106#define CONFIG_CONS_INDEX 1
107#define CONFIG_BAUDRATE 115200
108/*
109 * NS16550 Configuration
110 */
111#define CFG_NS16550
112#define CFG_NS16550_SERIAL
113
114#define CFG_NS16550_REG_SIZE 1
115
116#define CFG_NS16550_CLK 14745600
117
118#define CFG_UART_BASE 0xE0000000
119#define CFG_UART_SIZE 0x10000
120
121#define CFG_NS16550_COM1 (CFG_UART_BASE + 0x8000)
122
123/*
124 * select ethernet configuration
125 *
126 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
127 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
128 * for FCC)
129 *
130 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
131 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
132 * from CONFIG_COMMANDS to remove support for networking.
133 *
134 */
135#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
136#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
137#undef CONFIG_ETHER_NONE /* define if ether on something else */
138#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
139
140/*
141 * - Rx-CLK is CLK13
142 * - Tx-CLK is CLK14
143 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
144 * - Enable Full Duplex in FSMR
145 */
146# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
147# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
148# define CFG_CPMFCR_RAMTYPE 0
149# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
150
151
152/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
153#define CONFIG_8260_CLKIN 66666666 /* in Hz */
154
155#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
156#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
157
158#undef CONFIG_WATCHDOG /* watchdog disabled */
159
160#define CONFIG_TIMESTAMP /* Print image info with timestamp */
161
162#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
163
164#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
165 CFG_CMD_DHCP | \
166 CFG_CMD_NFS | \
167 CFG_CMD_NAND | \
168 CFG_CMD_I2C | \
169 CFG_CMD_SNTP )
170
171/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
172#include <cmd_confdefs.h>
173
174/*
175 * Miscellaneous configurable options
176 */
177#define CFG_LONGHELP /* undef to save memory */
178#define CFG_PROMPT "=> " /* Monitor Command Prompt */
179#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
180#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
181#else
182#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
183#endif
184#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
185#define CFG_MAXARGS 16 /* max number of command args */
186#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
187
188#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
189#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
190
191#define CFG_LOAD_ADDR 0x100000 /* default load address */
192
193#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
194
195#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
196
197#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
198
199/*
200 * For booting Linux, the board info and command line data
201 * have to be in the first 8 MB of memory, since this is
202 * the maximum mapped by the Linux kernel during initialization.
203 */
204#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
205
206
207/* What should the base address of the main FLASH be and how big is
208 * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
209 * The main FLASH is whichever is connected to *CS0.
210 */
211#define CFG_FLASH0_BASE 0xFFF00000
212#define CFG_FLASH0_SIZE 8
213
214/* Flash bank size (for preliminary settings)
215 */
216#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
217
218/*-----------------------------------------------------------------------
219 * FLASH organization
220 */
221#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
222#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
223
224#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
225#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
226
227/* Environment in flash */
228#define CFG_ENV_IS_IN_FLASH 1
229#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x60000)
230#define CFG_ENV_SIZE 0x20000
231#define CFG_ENV_SECT_SIZE 0x20000
232
233/*-----------------------------------------------------------------------
234 * NAND-FLASH stuff
235 *-----------------------------------------------------------------------
236 */
237#if (CONFIG_COMMANDS & CFG_CMD_NAND)
238
Marian Balakowicz6db39702006-04-08 19:08:06 +0200239#define CFG_NAND_LEGACY
wdenk9dd41a72005-05-12 22:48:09 +0000240#define CFG_NAND0_BASE 0xE1000000
241
242#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
243#define SECTORSIZE 512
244#define NAND_NO_RB
245
246#define ADDR_COLUMN 1
247#define ADDR_PAGE 2
248#define ADDR_COLUMN_PAGE 3
249
250#define NAND_ChipID_UNKNOWN 0x00
251#define NAND_MAX_FLOORS 1
252#define NAND_MAX_CHIPS 1
253
254#define NAND_DISABLE_CE(nand) do \
255{ \
256 *(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
257} while(0)
258
259#define NAND_ENABLE_CE(nand) do \
260{ \
261 *(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
262} while(0)
263
264#define NAND_CTL_CLRALE(nandptr) do \
265{ \
266 *(((volatile __u8 *)nandptr) + 0x8) = 0; \
267} while(0)
268
269#define NAND_CTL_SETALE(nandptr) do \
270{ \
271 *(((volatile __u8 *)nandptr) + 0x9) = 0; \
272} while(0)
273
274#define NAND_CTL_CLRCLE(nandptr) do \
275{ \
276 *(((volatile __u8 *)nandptr) + 0x8) = 0; \
277} while(0)
278
279#define NAND_CTL_SETCLE(nandptr) do \
280{ \
281 *(((volatile __u8 *)nandptr) + 0xa) = 0; \
282} while(0)
283
284#ifdef NAND_NO_RB
285/* constant delay (see also tR in the datasheet) */
286#define NAND_WAIT_READY(nand) do { \
287 udelay(12); \
288} while (0)
289#else
290/* use the R/B pin */
291#endif
292
293#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)
294#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)
295#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
296#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
297
298#endif /* CFG_CMD_NAND */
299
300/*-----------------------------------------------------------------------
301 * Hard Reset Configuration Words
302 *
303 * if you change bits in the HRCW, you must also change the CFG_*
304 * defines for the various registers affected by the HRCW e.g. changing
305 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
306 */
307#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
308
309/* no slaves so just fill with zeros */
310#define CFG_HRCW_SLAVE1 0
311#define CFG_HRCW_SLAVE2 0
312#define CFG_HRCW_SLAVE3 0
313#define CFG_HRCW_SLAVE4 0
314#define CFG_HRCW_SLAVE5 0
315#define CFG_HRCW_SLAVE6 0
316#define CFG_HRCW_SLAVE7 0
317
318/*-----------------------------------------------------------------------
319 * Internal Memory Mapped Register
320 */
321#define CFG_IMMR 0xF0000000
322
323/*-----------------------------------------------------------------------
324 * Definitions for initial stack pointer and data area (in DPRAM)
325 */
326#define CFG_INIT_RAM_ADDR CFG_IMMR
327#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
328#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
329#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
330#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
331
332/*-----------------------------------------------------------------------
333 * Start addresses for the final memory configuration
334 * (Set up by the startup code)
335 * Please note that CFG_SDRAM_BASE _must_ start at 0
336 *
337 * 60x SDRAM is mapped at CFG_SDRAM_BASE
338 */
339#define CFG_SDRAM_BASE 0x00000000
340#define CFG_FLASH_BASE CFG_FLASH0_BASE
341#define CFG_MONITOR_BASE TEXT_BASE
342#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
343#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
344
345/*
346 * Internal Definitions
347 *
348 * Boot Flags
349 */
350#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
351#define BOOTFLAG_WARM 0x02 /* Software reboot */
352
353
354/*-----------------------------------------------------------------------
355 * Cache Configuration
356 */
357#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
358#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
359# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
360#endif
361
362/*-----------------------------------------------------------------------
363 * HIDx - Hardware Implementation-dependent Registers 2-11
364 *-----------------------------------------------------------------------
365 * HID0 also contains cache control - initially enable both caches and
366 * invalidate contents, then the final state leaves only the instruction
367 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
368 * but Soft reset does not.
369 *
370 * HID1 has only read-only information - nothing to set.
371 */
372
373#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
374#define CFG_HID0_FINAL 0
375#define CFG_HID2 0
376
377/*-----------------------------------------------------------------------
378 * RMR - Reset Mode Register 5-5
379 *-----------------------------------------------------------------------
380 * turn on Checkstop Reset Enable
381 */
382#define CFG_RMR 0
383
384/*-----------------------------------------------------------------------
385 * BCR - Bus Configuration 4-25
386 *-----------------------------------------------------------------------
387 */
388#define CFG_BCR 0
389
390/*-----------------------------------------------------------------------
391 * SIUMCR - SIU Module Configuration 4-31
392 *-----------------------------------------------------------------------
393 */
394#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
395
396/*-----------------------------------------------------------------------
397 * SYPCR - System Protection Control 4-35
398 * SYPCR can only be written once after reset!
399 *-----------------------------------------------------------------------
400 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
401 */
402#if defined(CONFIG_WATCHDOG)
403#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
404 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
405#else
406#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
407 SYPCR_SWRI|SYPCR_SWP)
408#endif /* CONFIG_WATCHDOG */
409
410/*-----------------------------------------------------------------------
411 * TMCNTSC - Time Counter Status and Control 4-40
412 *-----------------------------------------------------------------------
413 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
414 * and enable Time Counter
415 */
416#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
417
418/*-----------------------------------------------------------------------
419 * PISCR - Periodic Interrupt Status and Control 4-42
420 *-----------------------------------------------------------------------
421 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
422 * Periodic timer
423 */
424#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
425
426/*-----------------------------------------------------------------------
427 * SCCR - System Clock Control 9-8
428 *-----------------------------------------------------------------------
429 * Ensure DFBRG is Divide by 16
430 */
431#define CFG_SCCR (0x00000028 | SCCR_DFBRG01)
432
433/*-----------------------------------------------------------------------
434 * RCCR - RISC Controller Configuration 13-7
435 *-----------------------------------------------------------------------
436 */
437#define CFG_RCCR 0
438
439/*
440 * Init Memory Controller:
441 *
442 * Bank Bus Machine PortSz Device
443 * ---- --- ------- ------ ------
444 * 0 60x GPCM 16 bit FLASH
445 * 1 60x GPCM 8 bit NAND
446 * 2 60x SDRAM 32 bit SDRAM
447 * 3 60x GPCM 8 bit UART
448 *
449 */
450
451#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
452
453/* Minimum mask to separate preliminary
454 * address ranges for CS[0:2]
455 */
456#define CFG_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */
457
458#define CFG_MPTPR 0x6600
459
460/*-----------------------------------------------------------------------------
461 * Address for Mode Register Set (MRS) command
462 *-----------------------------------------------------------------------------
463 */
464#define CFG_MRS_OFFS 0x00000110
465
466
467/* Bank 0 - FLASH
468 */
469#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
470 BRx_PS_8 |\
471 BRx_MS_GPCM_P |\
472 BRx_V)
473
474#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\
475 ORxG_SCY_6_CLK )
476
477#if (CONFIG_COMMANDS & CFG_CMD_NAND)
478/* Bank 1 - NAND Flash
479*/
480#define CFG_NAND_BASE CFG_NAND0_BASE
481#define CFG_NAND_SIZE 0x8000
482
483#define CFG_OR_TIMING_NAND 0x000036
484
485#define CFG_BR1_PRELIM ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
486#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND )
487#endif
488
489/* Bank 2 - 60x bus SDRAM
490 */
491#define CFG_PSRT 0x20
492#define CFG_LSRT 0x20
493
494#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
495 BRx_PS_32 |\
496 BRx_MS_SDRAM_P |\
497 BRx_V)
498
499#define CFG_OR2_PRELIM CFG_OR2
500
501
502/* SDRAM initialization values
503*/
504#define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
505 ORxS_BPD_4 |\
506 ORxS_ROWST_PBI0_A10 |\
507 ORxS_NUMR_12)
508
509#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\
510 PSDMR_BSMA_A15_A17 |\
511 PSDMR_SDA10_PBI0_A11 |\
512 PSDMR_RFRC_5_CLK |\
513 PSDMR_PRETOACT_2W |\
514 PSDMR_ACTTORW_2W |\
515 PSDMR_BL |\
516 PSDMR_LDOTOPRE_2C |\
517 PSDMR_WRC_3C |\
518 PSDMR_CL_3)
519
520/* Bank 3 - UART
521*/
522
523#define CFG_BR3_PRELIM ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )
524#define CFG_OR3_PRELIM (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
525
526#endif /* __CONFIG_H */