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wdenk81a88242002-10-26 15:22:42 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 * Gary Jennejohn <gj@denx.de>
6 * David Mueller <d.mueller@elsoft.ch>
7 *
8 * Configuation settings for the SAMSUNG SMDK2410 board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
wdenk81a88242002-10-26 15:22:42 +000033 * High Level Configuration Options
34 * (easy to change)
35 */
36#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
37#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
38#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
39
40/* input clock of PLL */
wdenk7f6c2cb2002-11-10 22:06:23 +000041#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
wdenk81a88242002-10-26 15:22:42 +000042
43
44#define USE_920T_MMU 1
45#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
46
47/*
48 * Size of malloc() pool
49 */
wdenk699b13a2002-11-03 18:03:52 +000050#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenka8c7c702003-12-06 19:49:23 +000051#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk81a88242002-10-26 15:22:42 +000052
53/*
54 * Hardware drivers
55 */
56#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
57#define CS8900_BASE 0x19000300
58#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
59
60/*
61 * select serial console configuration
62 */
63#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
64
wdenk48b42612003-06-19 23:01:32 +000065/************************************************************
66 * RTC
67 ************************************************************/
68#define CONFIG_RTC_S3C24X0 1
69
wdenk81a88242002-10-26 15:22:42 +000070/* allow to overwrite serial and ethaddr */
71#define CONFIG_ENV_OVERWRITE
72
73#define CONFIG_BAUDRATE 115200
74
wdenk48b42612003-06-19 23:01:32 +000075/***********************************************************
76 * Command definition
77 ***********************************************************/
78#define CONFIG_COMMANDS \
79 (CONFIG_CMD_DFL | \
80 CFG_CMD_CACHE | \
81 /*CFG_CMD_NAND |*/ \
82 /*CFG_CMD_EEPROM |*/ \
83 /*CFG_CMD_I2C |*/ \
84 /*CFG_CMD_USB |*/ \
85 CFG_CMD_REGINFO | \
86 CFG_CMD_DATE | \
87 CFG_CMD_ELF)
wdenk81a88242002-10-26 15:22:42 +000088
89/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
90#include <cmd_confdefs.h>
91
92#define CONFIG_BOOTDELAY 3
93/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
94/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */
95#define CONFIG_NETMASK 255.255.255.0
96#define CONFIG_IPADDR 10.0.0.110
97#define CONFIG_SERVERIP 10.0.0.1
98/*#define CONFIG_BOOTFILE "elinos-lart" */
99/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
100
101#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
102#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
103/* what's this ? it's not used anywhere */
104#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
105#endif
106
107/*
108 * Miscellaneous configurable options
109 */
110#define CFG_LONGHELP /* undef to save memory */
111#define CFG_PROMPT "SMDK2410 # " /* Monitor Command Prompt */
112#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
113#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
114#define CFG_MAXARGS 16 /* max number of command args */
115#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
116
117#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
118#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
119
120#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
121
122#define CFG_LOAD_ADDR 0x33000000 /* default load address */
123
124/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
125/* it to wrap 100 times (total 1562500) to get 1 sec. */
126#define CFG_HZ 1562500
127
128/* valid baudrates */
129#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
130
131/*-----------------------------------------------------------------------
132 * Stack sizes
133 *
134 * The stack sizes are set up in start.S using the settings below
135 */
136#define CONFIG_STACKSIZE (128*1024) /* regular stack */
137#ifdef CONFIG_USE_IRQ
138#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
139#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
140#endif
141
142/*-----------------------------------------------------------------------
143 * Physical Memory Map
144 */
145#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
146#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
147#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
148
149#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
150
151#define CFG_FLASH_BASE PHYS_FLASH_1
152
153/*-----------------------------------------------------------------------
154 * FLASH and environment organization
155 */
156
157#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
158#if 0
159#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
160#endif
161
162#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
163#ifdef CONFIG_AMD_LV800
164#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
165#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
166#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
167#endif
168#ifdef CONFIG_AMD_LV400
169#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
170#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
171#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
172#endif
173
174/* timeout values are in ticks */
175#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
176#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
177
178#define CFG_ENV_IS_IN_FLASH 1
179#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
180
181#endif /* __CONFIG_H */