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wdenkfe8c2802002-11-03 00:38:21 +00001/*
wdenk10a36a92004-07-10 23:02:23 +00002 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
wdenkfe8c2802002-11-03 00:38:21 +00004 *
wdenk10a36a92004-07-10 23:02:23 +00005 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuration settings for the WindRiver SBC8260 board.
14 * See http://www.windriver.com/products/html/sbc8260.html
wdenkfe8c2802002-11-03 00:38:21 +000015 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
wdenk10a36a92004-07-10 23:02:23 +000038/* Enable debug prints */
39#undef DEBUG /* General debug */
40#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
wdenkfe8c2802002-11-03 00:38:21 +000041
wdenk10a36a92004-07-10 23:02:23 +000042/*****************************************************************************
43 *
44 * These settings must match the way _your_ board is set up
45 *
46 *****************************************************************************/
wdenkfe8c2802002-11-03 00:38:21 +000047
wdenk10a36a92004-07-10 23:02:23 +000048/* What is the oscillator's (UX2) frequency in Hz? */
49#define CONFIG_8260_CLKIN (66 * 1000 * 1000)
wdenk466b7412004-07-10 22:35:59 +000050
51/*-----------------------------------------------------------------------
wdenk10a36a92004-07-10 23:02:23 +000052 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
53 *-----------------------------------------------------------------------
54 * What should MODCK_H be? It is dependent on the oscillator
55 * frequency, MODCK[1-3], and desired CPM and core frequencies.
56 * Here are some example values (all frequencies are in MHz):
57 *
58 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
59 * ------- ---------- --- --- ---- ----- ----- -----
60 * 0x1 0x5 33 100 133 Open Close Open
61 * 0x1 0x6 33 100 166 Open Open Close
62 * 0x1 0x7 33 100 200 Open Open Open
63 *
64 * 0x2 0x2 33 133 133 Close Open Close
65 * 0x2 0x3 33 133 166 Close Open Open
66 * 0x2 0x4 33 133 200 Open Close Close
67 * 0x2 0x5 33 133 233 Open Close Open
68 * 0x2 0x6 33 133 266 Open Open Close
69 *
70 * 0x5 0x5 66 133 133 Open Close Open
71 * 0x5 0x6 66 133 166 Open Open Close
72 * 0x5 0x7 66 133 200 Open Open Open
73 * 0x6 0x0 66 133 233 Close Close Close
74 * 0x6 0x1 66 133 266 Close Close Open
75 * 0x6 0x2 66 133 300 Close Open Close
76 */
77#define CFG_SBC_MODCK_H 0x05
78
79/* Define this if you want to boot from 0x00000100. If you don't define
80 * this, you will need to program the bootloader to 0xfff00000, and
81 * get the hardware reset config words at 0xfe000000. The simplest
82 * way to do that is to program the bootloader at both addresses.
83 * It is suggested that you just let U-Boot live at 0x00000000.
84 */
85#define CFG_SBC_BOOT_LOW 1
86
87/* What should the base address of the main FLASH be and how big is
88 * it (in MBytes)? This must contain TEXT_BASE from board/sbc8260/config.mk
89 * The main FLASH is whichever is connected to *CS0. U-Boot expects
90 * this to be the SIMM.
91 */
92#define CFG_FLASH0_BASE 0x40000000
93#define CFG_FLASH0_SIZE 4
94
95/* What should the base address of the secondary FLASH be and how big
96 * is it (in Mbytes)? The secondary FLASH is whichever is connected
97 * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
98 * want it enabled, don't define these constants.
99 */
100#define CFG_FLASH1_BASE 0x60000000
101#define CFG_FLASH1_SIZE 2
102
103/* What should be the base address of SDRAM DIMM and how big is
104 * it (in Mbytes)?
105*/
106#define CFG_SDRAM0_BASE 0x00000000
107#define CFG_SDRAM0_SIZE 64
108
109/* What should be the base address of the LEDs and switch S0?
110 * If you don't want them enabled, don't define this.
111 */
112#define CFG_LED_BASE 0xa0000000
113
114
115/*
116 * SBC8260 with 16 MB DIMM:
117 *
118 * 0x0000 0000 Exception Vector code, 8k
119 * :
120 * 0x0000 1FFF
121 * 0x0000 2000 Free for Application Use
122 * :
123 * :
124 *
125 * :
126 * :
127 * 0x00F5 FF30 Monitor Stack (Growing downward)
128 * Monitor Stack Buffer (0x80)
129 * 0x00F5 FFB0 Board Info Data
130 * 0x00F6 0000 Malloc Arena
131 * : CFG_ENV_SECT_SIZE, 256k
132 * : CFG_MALLOC_LEN, 128k
133 * 0x00FC 0000 RAM Copy of Monitor Code
134 * : CFG_MONITOR_LEN, 256k
135 * 0x00FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
wdenk466b7412004-07-10 22:35:59 +0000136 */
137
wdenk10a36a92004-07-10 23:02:23 +0000138/*
139 * SBC8260 with 64 MB DIMM:
140 *
141 * 0x0000 0000 Exception Vector code, 8k
142 * :
143 * 0x0000 1FFF
144 * 0x0000 2000 Free for Application Use
145 * :
146 * :
147 *
148 * :
149 * :
150 * 0x03F5 FF30 Monitor Stack (Growing downward)
151 * Monitor Stack Buffer (0x80)
152 * 0x03F5 FFB0 Board Info Data
153 * 0x03F6 0000 Malloc Arena
154 * : CFG_ENV_SECT_SIZE, 256k
155 * : CFG_MALLOC_LEN, 128k
156 * 0x03FC 0000 RAM Copy of Monitor Code
157 * : CFG_MONITOR_LEN, 256k
158 * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
159 */
160
161
162/*
163 * select serial console configuration
164 *
165 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
166 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
167 * for SCC).
168 *
169 * if CONFIG_CONS_NONE is defined, then the serial console routines must
170 * defined elsewhere.
171 */
172#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
173#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
174#undef CONFIG_CONS_NONE /* define if console on neither */
175#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
176
177/*
178 * select ethernet configuration
179 *
180 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
181 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
182 * for FCC)
183 *
184 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500185 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk10a36a92004-07-10 23:02:23 +0000186 */
187
188#undef CONFIG_ETHER_ON_SCC
189#define CONFIG_ETHER_ON_FCC
190#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
191
192#ifdef CONFIG_ETHER_ON_SCC
193#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
194#endif /* CONFIG_ETHER_ON_SCC */
195
196#ifdef CONFIG_ETHER_ON_FCC
197#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
198#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
199#define CONFIG_MII /* MII PHY management */
200#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
201/*
202 * Port pins used for bit-banged MII communictions (if applicable).
203 */
204#define MDIO_PORT 2 /* Port C */
205#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
206#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
207#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
208
209#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
210 else iop->pdat &= ~0x00400000
211
212#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
213 else iop->pdat &= ~0x00200000
214
215#define MIIDELAY udelay(1)
216#endif /* CONFIG_ETHER_ON_FCC */
217
218#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
219
220/*
221 * - RX clk is CLK11
222 * - TX clk is CLK12
223 */
224# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
225
226#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
227
228/*
229 * - Rx-CLK is CLK13
230 * - Tx-CLK is CLK14
231 * - Select bus for bd/buffers (see 28-13)
232 * - Enable Full Duplex in FSMR
233 */
234# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
235# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
236# define CFG_CPMFCR_RAMTYPE 0
237# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
238
239#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
240
241/*
242 * Select SPI support configuration
243 */
244#undef CONFIG_SPI /* Disable SPI driver */
245
246/*
247 * Select i2c support configuration
248 *
249 * Supported configurations are {none, software, hardware} drivers.
250 * If the software driver is chosen, there are some additional
251 * configuration items that the driver uses to drive the port pins.
252 */
253#undef CONFIG_HARD_I2C /* I2C with hardware support */
254#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
255#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
256#define CFG_I2C_SLAVE 0x7F
257
258/*
259 * Software (bit-bang) I2C driver configuration
260 */
261#ifdef CONFIG_SOFT_I2C
262#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
263#define I2C_ACTIVE (iop->pdir |= 0x00010000)
264#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
265#define I2C_READ ((iop->pdat & 0x00010000) != 0)
266#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
267 else iop->pdat &= ~0x00010000
268#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
269 else iop->pdat &= ~0x00020000
270#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
271#endif /* CONFIG_SOFT_I2C */
272
273
274/* Define this to reserve an entire FLASH sector (256 KB) for
275 * environment variables. Otherwise, the environment will be
276 * put in the same sector as U-Boot, and changing variables
277 * will erase U-Boot temporarily
278 */
279#define CFG_ENV_IN_OWN_SECT 1
280
281/* Define to allow the user to overwrite serial and ethaddr */
282#define CONFIG_ENV_OVERWRITE
283
284/* What should the console's baud rate be? */
285#define CONFIG_BAUDRATE 9600
286
287/* Ethernet MAC address
288 * Note: We are using the EST Corporation OUI (00:a0:1e:xx:xx:xx)
289 * http://standards.ieee.org/regauth/oui/index.shtml
290 */
291#define CONFIG_ETHADDR 00:a0:1e:a8:7b:cb
292
293/*
294 * Define this to set the last octet of the ethernet address from the
295 * DS0-DS7 switch and light the LEDs with the result. The DS0-DS7
296 * switch and the LEDs are backwards with respect to each other. DS7
297 * is on the board edge side of both the LED strip and the DS0-DS7
298 * switch.
299 */
300#undef CONFIG_MISC_INIT_R
301
302/* Set to a positive value to delay for running BOOTCOMMAND */
303#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
304
305/* Be selective on what keys can delay or stop the autoboot process
306 * To stop use: " "
307 */
308#undef CONFIG_AUTOBOOT_KEYED
309#ifdef CONFIG_AUTOBOOT_KEYED
310# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
311# define CONFIG_AUTOBOOT_STOP_STR " "
312# undef CONFIG_AUTOBOOT_DELAY_STR
313# define DEBUG_BOOTKEYS 0
wdenk466b7412004-07-10 22:35:59 +0000314#endif
wdenk466b7412004-07-10 22:35:59 +0000315
wdenk10a36a92004-07-10 23:02:23 +0000316/* Define this to contain any number of null terminated strings that
317 * will be part of the default enviroment compiled into the boot image.
318 *
319 * Variable Usage
320 * -------------- -------------------------------------------------------
321 * serverip server IP address
322 * ipaddr my IP address
323 * reprog Reload flash with a new copy of U-Boot
324 * zapenv Erase the environment area in flash
325 * root-on-initrd Set the bootcmd variable to allow booting of an initial
326 * ram disk.
327 * root-on-nfs Set the bootcmd variable to allow booting of a NFS
328 * mounted root filesystem.
329 * boot-hook Convenient stub to do something useful before the
330 * bootm command is executed.
331 *
332 * Example usage of root-on-initrd and root-on-nfs :
333 *
334 * Note: The lines have been wrapped to improved its readability.
335 *
336 * => printenv bootcmd
337 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100338 * nfsroot=${serverip}:${rootpath}
339 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
wdenk10a36a92004-07-10 23:02:23 +0000340 *
341 * => run root-on-initrd
342 * => printenv bootcmd
343 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/ram0 rw
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100344 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
wdenk10a36a92004-07-10 23:02:23 +0000345 *
346 * => run root-on-nfs
347 * => printenv bootcmd
348 * bootcmd=version;echo;bootp;setenv bootargs root=/dev/nfs rw
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100349 * nfsroot=${serverip}:${rootpath}
350 * ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;run boot-hook;bootm
wdenk10a36a92004-07-10 23:02:23 +0000351 *
352 */
353#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkb9283e22004-07-11 21:49:42 +0000354 "serverip=192.168.123.205\0" \
wdenk10a36a92004-07-10 23:02:23 +0000355 "ipaddr=192.168.123.213\0" \
356 "reprog="\
357 "bootp;" \
358 "tftpboot 0x140000 /bdi2000/u-boot.bin;" \
359 "protect off 1:0;" \
360 "erase 1:0;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100361 "cp.b 140000 40000000 ${filesize};" \
wdenk10a36a92004-07-10 23:02:23 +0000362 "protect on 1:0\0" \
363 "zapenv="\
364 "protect off 1:1;" \
365 "erase 1:1;" \
366 "protect on 1:1\0" \
367 "root-on-initrd="\
368 "setenv bootcmd "\
369 "version;" \
370 "echo;" \
371 "bootp;" \
372 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100373 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000374 "run boot-hook;" \
375 "bootm\0" \
376 "root-on-nfs="\
377 "setenv bootcmd "\
378 "version;" \
379 "echo;" \
380 "bootp;" \
381 "setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100382 "nfsroot=${serverip}:${rootpath} " \
383 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000384 "run boot-hook;" \
385 "bootm\0" \
386 "boot-hook=echo\0"
wdenk466b7412004-07-10 22:35:59 +0000387
wdenk10a36a92004-07-10 23:02:23 +0000388/* Define a command string that is automatically executed when no character
389 * is read on the console interface withing "Boot Delay" after reset.
390 */
391#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
392#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenk466b7412004-07-10 22:35:59 +0000393
wdenk10a36a92004-07-10 23:02:23 +0000394#ifdef CONFIG_BOOT_ROOT_INITRD
395#define CONFIG_BOOTCOMMAND \
396 "version;" \
397 "echo;" \
398 "bootp;" \
399 "setenv bootargs root=/dev/ram0 rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100400 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000401 "bootm"
402#endif /* CONFIG_BOOT_ROOT_INITRD */
403
404#ifdef CONFIG_BOOT_ROOT_NFS
405#define CONFIG_BOOTCOMMAND \
406 "version;" \
407 "echo;" \
408 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100409 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
410 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk10a36a92004-07-10 23:02:23 +0000411 "bootm"
412#endif /* CONFIG_BOOT_ROOT_NFS */
413
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500414/*
415 * BOOTP options
wdenk10a36a92004-07-10 23:02:23 +0000416 */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500417#define CONFIG_BOOTP_SUBNETMASK
418#define CONFIG_BOOTP_GATEWAY
419#define CONFIG_BOOTP_HOSTNAME
420#define CONFIG_BOOTP_BOOTPATH
421#define CONFIG_BOOTP_BOOTFILESIZE
422#define CONFIG_BOOTP_DNS
423#define CONFIG_BOOTP_DNS2
424#define CONFIG_BOOTP_SEND_HOSTNAME
425
wdenk10a36a92004-07-10 23:02:23 +0000426
427/* undef this to save memory */
428#define CFG_LONGHELP
429
430/* Monitor Command Prompt */
431#define CFG_PROMPT "=> "
432
433#undef CFG_HUSH_PARSER
434#ifdef CFG_HUSH_PARSER
435#define CFG_PROMPT_HUSH_PS2 "> "
436#endif
437
438/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
439 * of an image is printed by image commands like bootm or iminfo.
440 */
441#define CONFIG_TIMESTAMP
442
443/* If this variable is defined, an environment variable named "ver"
444 * is created by U-Boot showing the U-Boot version.
445 */
446#define CONFIG_VERSION_VARIABLE
447
Jon Loeliger866e3082007-07-04 22:30:58 -0500448
449/*
450 * Command line configuration.
451 */
452#include <config_cmd_default.h>
453
454#define CONFIG_CMD_ASKENV
455#define CONFIG_CMD_ELF
456#define CONFIG_CMD_I2C
457#define CONFIG_CMD_IMMAP
458#define CONFIG_CMD_PING
459#define CONFIG_CMD_REGINFO
460#define CONFIG_CMD_SDRAM
461
462#undef CONFIG_CMD_KGDB
463
464#if defined(CONFIG_ETHER_ON_FCC)
465 #define CONFIG_CMD_CMD_MII
466#endif
467
wdenk466b7412004-07-10 22:35:59 +0000468
wdenk10a36a92004-07-10 23:02:23 +0000469#undef CONFIG_WATCHDOG /* disable the watchdog */
wdenk466b7412004-07-10 22:35:59 +0000470
wdenk10a36a92004-07-10 23:02:23 +0000471/* Where do the internal registers live? */
472#define CFG_IMMR 0xF0000000
wdenk466b7412004-07-10 22:35:59 +0000473
wdenk10a36a92004-07-10 23:02:23 +0000474/*****************************************************************************
475 *
476 * You should not have to modify any of the following settings
477 *
478 *****************************************************************************/
wdenk466b7412004-07-10 22:35:59 +0000479
wdenk10a36a92004-07-10 23:02:23 +0000480#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
481#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500482#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk466b7412004-07-10 22:35:59 +0000483
wdenkfe8c2802002-11-03 00:38:21 +0000484
485/*
486 * Miscellaneous configurable options
487 */
Jon Loeliger866e3082007-07-04 22:30:58 -0500488#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000489# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000490#else
wdenk10a36a92004-07-10 23:02:23 +0000491# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000492#endif
wdenk10a36a92004-07-10 23:02:23 +0000493
494/* Print Buffer Size */
495#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
496
497#define CFG_MAXARGS 32 /* max number of command args */
498
499#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
500
501#define CFG_LOAD_ADDR 0x400000 /* default load address */
502#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
503
504#define CFG_ALT_MEMTEST /* Select full-featured memory test */
505#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
506 /* the exception vector table */
507 /* to the end of the DRAM */
508 /* less monitor and malloc area */
509#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
510#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
511 + CFG_MALLOC_LEN \
512 + CFG_ENV_SECT_SIZE \
513 + CFG_STACK_USAGE )
514
515#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
516 - CFG_MEM_END_USAGE )
517
518/* valid baudrates */
519#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
520
521/*
522 * Low Level Configuration Settings
523 * (address mappings, register initial values, etc.)
524 * You should know what you are doing if you make changes here.
525 */
526
527#define CFG_FLASH_BASE CFG_FLASH0_BASE
528#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
529#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
530#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
531
532/*-----------------------------------------------------------------------
533 * Hard Reset Configuration Words
534 */
535#if defined(CFG_SBC_BOOT_LOW)
536# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
537#else
538# define CFG_SBC_HRCW_BOOT_FLAGS (0)
539#endif /* defined(CFG_SBC_BOOT_LOW) */
540
541/* get the HRCW ISB field from CFG_IMMR */
542#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
543 ((CFG_IMMR & 0x01000000) >> 7) | \
544 ((CFG_IMMR & 0x00100000) >> 4) )
545
546#define CFG_HRCW_MASTER ( HRCW_BPS11 | \
547 HRCW_DPPC11 | \
548 CFG_SBC_HRCW_IMMR | \
549 HRCW_MMR00 | \
550 HRCW_LBPC11 | \
551 HRCW_APPC10 | \
552 HRCW_CS10PC00 | \
553 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
554 CFG_SBC_HRCW_BOOT_FLAGS )
555
556/* no slaves */
557#define CFG_HRCW_SLAVE1 0
558#define CFG_HRCW_SLAVE2 0
559#define CFG_HRCW_SLAVE3 0
560#define CFG_HRCW_SLAVE4 0
561#define CFG_HRCW_SLAVE5 0
562#define CFG_HRCW_SLAVE6 0
563#define CFG_HRCW_SLAVE7 0
564
565/*-----------------------------------------------------------------------
566 * Definitions for initial stack pointer and data area (in DPRAM)
567 */
568#define CFG_INIT_RAM_ADDR CFG_IMMR
569#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
570#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
571#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
572#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
573
574/*-----------------------------------------------------------------------
575 * Start addresses for the final memory configuration
576 * (Set up by the startup code)
577 * Please note that CFG_SDRAM_BASE _must_ start at 0
578 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
579 */
580#define CFG_MONITOR_BASE CFG_FLASH0_BASE
581
582#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
583# define CFG_RAMBOOT
584#endif
585
586#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
587#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000588
589/*
590 * For booting Linux, the board info and command line data
591 * have to be in the first 8 MB of memory, since this is
592 * the maximum mapped by the Linux kernel during initialization.
593 */
wdenk10a36a92004-07-10 23:02:23 +0000594#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000595
wdenk10a36a92004-07-10 23:02:23 +0000596/*-----------------------------------------------------------------------
597 * FLASH and environment organization
598 */
599#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
600#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
601
602#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
603#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
604
605#ifndef CFG_RAMBOOT
606# define CFG_ENV_IS_IN_FLASH 1
607
608# ifdef CFG_ENV_IN_OWN_SECT
609# define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
610# define CFG_ENV_SECT_SIZE 0x40000
611# else
612# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
613# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
614# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
615# endif /* CFG_ENV_IN_OWN_SECT */
616
617#else
618# define CFG_ENV_IS_IN_NVRAM 1
619# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
620# define CFG_ENV_SIZE 0x200
621#endif /* CFG_RAMBOOT */
622
623/*-----------------------------------------------------------------------
624 * Cache Configuration
625 */
626#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
627
Jon Loeliger866e3082007-07-04 22:30:58 -0500628#if defined(CONFIG_CMD_KGDB)
wdenk10a36a92004-07-10 23:02:23 +0000629# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkfe8c2802002-11-03 00:38:21 +0000630#endif
631
wdenk10a36a92004-07-10 23:02:23 +0000632/*-----------------------------------------------------------------------
633 * HIDx - Hardware Implementation-dependent Registers 2-11
634 *-----------------------------------------------------------------------
635 * HID0 also contains cache control - initially enable both caches and
636 * invalidate contents, then the final state leaves only the instruction
637 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
638 * but Soft reset does not.
639 *
640 * HID1 has only read-only information - nothing to set.
641 */
642#define CFG_HID0_INIT (HID0_ICE |\
643 HID0_DCE |\
644 HID0_ICFI |\
645 HID0_DCI |\
646 HID0_IFEM |\
647 HID0_ABE)
648
649#define CFG_HID0_FINAL (HID0_ICE |\
650 HID0_IFEM |\
651 HID0_ABE |\
652 HID0_EMCP)
653#define CFG_HID2 0
654
655/*-----------------------------------------------------------------------
656 * RMR - Reset Mode Register
657 *-----------------------------------------------------------------------
658 */
659#define CFG_RMR 0
660
661/*-----------------------------------------------------------------------
662 * BCR - Bus Configuration 4-25
663 *-----------------------------------------------------------------------
664 */
665#define CFG_BCR (BCR_ETM)
666
667/*-----------------------------------------------------------------------
668 * SIUMCR - SIU Module Configuration 4-31
669 *-----------------------------------------------------------------------
670 */
671
672#define CFG_SIUMCR (SIUMCR_DPPC11 |\
673 SIUMCR_L2CPC00 |\
674 SIUMCR_APPC10 |\
675 SIUMCR_MMR00)
676
677
678/*-----------------------------------------------------------------------
679 * SYPCR - System Protection Control 11-9
680 * SYPCR can only be written once after reset!
681 *-----------------------------------------------------------------------
682 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
683 */
684#if defined(CONFIG_WATCHDOG)
685#define CFG_SYPCR (SYPCR_SWTC |\
686 SYPCR_BMT |\
687 SYPCR_PBME |\
688 SYPCR_LBME |\
689 SYPCR_SWRI |\
690 SYPCR_SWP |\
691 SYPCR_SWE)
692#else
693#define CFG_SYPCR (SYPCR_SWTC |\
694 SYPCR_BMT |\
695 SYPCR_PBME |\
696 SYPCR_LBME |\
697 SYPCR_SWRI |\
698 SYPCR_SWP)
699#endif /* CONFIG_WATCHDOG */
700
701/*-----------------------------------------------------------------------
702 * TMCNTSC - Time Counter Status and Control 4-40
703 *-----------------------------------------------------------------------
704 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
705 * and enable Time Counter
706 */
707#define CFG_TMCNTSC (TMCNTSC_SEC |\
708 TMCNTSC_ALR |\
709 TMCNTSC_TCF |\
710 TMCNTSC_TCE)
711
712/*-----------------------------------------------------------------------
713 * PISCR - Periodic Interrupt Status and Control 4-42
714 *-----------------------------------------------------------------------
715 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
716 * Periodic timer
717 */
718#define CFG_PISCR (PISCR_PS |\
719 PISCR_PTF |\
720 PISCR_PTE)
721
722/*-----------------------------------------------------------------------
723 * SCCR - System Clock Control 9-8
724 *-----------------------------------------------------------------------
725 */
726#define CFG_SCCR 0
727
728/*-----------------------------------------------------------------------
729 * RCCR - RISC Controller Configuration 13-7
730 *-----------------------------------------------------------------------
731 */
732#define CFG_RCCR 0
733
734/*
735 * Initialize Memory Controller:
736 *
737 * Bank Bus Machine PortSz Device
738 * ---- --- ------- ------ ------
739 * 0 60x GPCM 32 bit FLASH (SIMM - 4MB) *
740 * 1 60x GPCM 32 bit FLASH (SIMM - Unused)
741 * 2 60x SDRAM 64 bit SDRAM (DIMM - 16MB or 64MB)
742 * 3 60x SDRAM 64 bit SDRAM (DIMM - Unused)
743 * 4 Local SDRAM 32 bit SDRAM (on board - 4MB)
744 * 5 60x GPCM 8 bit EEPROM (8KB)
745 * 6 60x GPCM 8 bit FLASH (on board - 2MB) *
746 * 7 60x GPCM 8 bit LEDs, switches
747 *
748 * (*) This configuration requires the SBC8260 be configured
749 * so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
750 * the on board FLASH. In other words, JP24 should have
751 * pins 1 and 2 jumpered and pins 3 and 4 jumpered.
752 *
753 */
754
755/*-----------------------------------------------------------------------
756 * BR0,BR1 - Base Register
757 * Ref: Section 10.3.1 on page 10-14
758 * OR0,OR1 - Option Register
759 * Ref: Section 10.3.2 on page 10-18
760 *-----------------------------------------------------------------------
761 */
762
763/* Bank 0,1 - FLASH SIMM
764 *
765 * This expects the FLASH SIMM to be connected to *CS0
766 * It consists of 4 AM29F080B parts.
767 *
768 * Note: For the 4 MB SIMM, *CS1 is unused.
769 */
770
771/* BR0 is configured as follows:
772 *
773 * - Base address of 0x40000000
774 * - 32 bit port size
775 * - Data errors checking is disabled
776 * - Read and write access
777 * - GPCM 60x bus
778 * - Access are handled by the memory controller according to MSEL
779 * - Not used for atomic operations
780 * - No data pipelining is done
781 * - Valid
782 */
783#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
784 BRx_PS_32 |\
785 BRx_MS_GPCM_P |\
786 BRx_V)
787
788/* OR0 is configured as follows:
789 *
790 * - 4 MB
791 * - *BCTL0 is asserted upon access to the current memory bank
792 * - *CW / *WE are negated a quarter of a clock earlier
793 * - *CS is output at the same time as the address lines
794 * - Uses a clock cycle length of 5
795 * - *PSDVAL is generated internally by the memory controller
796 * unless *GTA is asserted earlier externally.
797 * - Relaxed timing is generated by the GPCM for accesses
798 * initiated to this memory region.
799 * - One idle clock is inserted between a read access from the
800 * current bank and the next access.
801 */
802#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
803 ORxG_CSNT |\
804 ORxG_ACS_DIV1 |\
805 ORxG_SCY_5_CLK |\
806 ORxG_TRLX |\
807 ORxG_EHTR)
808
809/*-----------------------------------------------------------------------
810 * BR2,BR3 - Base Register
811 * Ref: Section 10.3.1 on page 10-14
812 * OR2,OR3 - Option Register
813 * Ref: Section 10.3.2 on page 10-16
814 *-----------------------------------------------------------------------
815 */
816
817/* Bank 2,3 - SDRAM DIMM
818 *
819 * 16MB DIMM: P/N
820 * 64MB DIMM: P/N 1W-8864X8-4-P1-EST
821 *
822 * Note: *CS3 is unused for this DIMM
823 */
824
825/* With a 16 MB or 64 MB DIMM, the BR2 is configured as follows:
826 *
827 * - Base address of 0x00000000
828 * - 64 bit port size (60x bus only)
829 * - Data errors checking is disabled
830 * - Read and write access
831 * - SDRAM 60x bus
832 * - Access are handled by the memory controller according to MSEL
833 * - Not used for atomic operations
834 * - No data pipelining is done
835 * - Valid
836 */
837#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
838 BRx_PS_64 |\
839 BRx_MS_SDRAM_P |\
840 BRx_V)
841
842#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
843 BRx_PS_64 |\
844 BRx_MS_SDRAM_P |\
845 BRx_V)
846
847/* With a 16 MB DIMM, the OR2 is configured as follows:
848 *
849 * - 16 MB
850 * - 2 internal banks per device
851 * - Row start address bit is A9 with PSDMR[PBI] = 0
852 * - 11 row address lines
853 * - Back-to-back page mode
854 * - Internal bank interleaving within save device enabled
855 */
856#if (CFG_SDRAM0_SIZE == 16)
857#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
858 ORxS_BPD_2 |\
859 ORxS_ROWST_PBI0_A9 |\
860 ORxS_NUMR_11)
861#endif
862
863/* With a 64 MB DIMM, the OR2 is configured as follows:
864 *
865 * - 64 MB
866 * - 4 internal banks per device
867 * - Row start address bit is A8 with PSDMR[PBI] = 0
868 * - 12 row address lines
869 * - Back-to-back page mode
870 * - Internal bank interleaving within save device enabled
871 */
872#if (CFG_SDRAM0_SIZE == 64)
873#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
874 ORxS_BPD_4 |\
875 ORxS_ROWST_PBI0_A8 |\
876 ORxS_NUMR_12)
877#endif
878
879/*-----------------------------------------------------------------------
880 * PSDMR - 60x Bus SDRAM Mode Register
881 * Ref: Section 10.3.3 on page 10-21
882 *-----------------------------------------------------------------------
883 */
884
885/* Address that the DIMM SPD memory lives at.
886 */
887#define SDRAM_SPD_ADDR 0x54
888
889#if (CFG_SDRAM0_SIZE == 16)
890/* With a 16 MB DIMM, the PSDMR is configured as follows:
891 *
892 * - Bank Based Interleaving,
893 * - Refresh Enable,
894 * - Address Multiplexing where A5 is output on A14 pin
895 * (A6 on A15, and so on),
896 * - use address pins A16-A18 as bank select,
897 * - A9 is output on SDA10 during an ACTIVATE command,
898 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
899 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
900 * is 3 clocks,
901 * - earliest timing for READ/WRITE command after ACTIVATE command is
902 * 2 clocks,
903 * - earliest timing for PRECHARGE after last data was read is 1 clock,
904 * - earliest timing for PRECHARGE after last data was written is 1 clock,
905 * - CAS Latency is 2.
906 */
907#define CFG_PSDMR (PSDMR_RFEN |\
908 PSDMR_SDAM_A14_IS_A5 |\
909 PSDMR_BSMA_A16_A18 |\
910 PSDMR_SDA10_PBI0_A9 |\
911 PSDMR_RFRC_7_CLK |\
912 PSDMR_PRETOACT_3W |\
913 PSDMR_ACTTORW_2W |\
914 PSDMR_LDOTOPRE_1C |\
915 PSDMR_WRC_1C |\
916 PSDMR_CL_2)
917#endif
918
919#if (CFG_SDRAM0_SIZE == 64)
920/* With a 64 MB DIMM, the PSDMR is configured as follows:
921 *
922 * - Bank Based Interleaving,
923 * - Refresh Enable,
924 * - Address Multiplexing where A5 is output on A14 pin
925 * (A6 on A15, and so on),
926 * - use address pins A14-A16 as bank select,
927 * - A9 is output on SDA10 during an ACTIVATE command,
928 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
929 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
930 * is 3 clocks,
931 * - earliest timing for READ/WRITE command after ACTIVATE command is
932 * 2 clocks,
933 * - earliest timing for PRECHARGE after last data was read is 1 clock,
934 * - earliest timing for PRECHARGE after last data was written is 1 clock,
935 * - CAS Latency is 2.
936 */
937#define CFG_PSDMR (PSDMR_RFEN |\
938 PSDMR_SDAM_A14_IS_A5 |\
939 PSDMR_BSMA_A14_A16 |\
940 PSDMR_SDA10_PBI0_A9 |\
941 PSDMR_RFRC_7_CLK |\
942 PSDMR_PRETOACT_3W |\
943 PSDMR_ACTTORW_2W |\
944 PSDMR_LDOTOPRE_1C |\
945 PSDMR_WRC_1C |\
946 PSDMR_CL_2)
947#endif
948
949/*
950 * Shoot for approximately 1MHz on the prescaler.
951 */
952#if (CONFIG_8260_CLKIN == (66 * 1000 * 1000))
953#define CFG_MPTPR MPTPR_PTP_DIV64
954#elif (CONFIG_8260_CLKIN == (33 * 1000 * 1000))
955#define CFG_MPTPR MPTPR_PTP_DIV32
956#else
957#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
958#define CFG_MPTPR MPTPR_PTP_DIV32
959#endif
960#define CFG_PSRT 14
961
962
963/* Bank 4 - On board SDRAM
964 *
965 * This is not implemented yet.
966 */
967
968/*-----------------------------------------------------------------------
969 * BR6 - Base Register
970 * Ref: Section 10.3.1 on page 10-14
971 * OR6 - Option Register
972 * Ref: Section 10.3.2 on page 10-18
973 *-----------------------------------------------------------------------
974 */
975
976/* Bank 6 - On board FLASH
977 *
978 * This expects the on board FLASH SIMM to be connected to *CS6
979 * It consists of 1 AM29F016A part.
980 */
981#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
982
983/* BR6 is configured as follows:
984 *
985 * - Base address of 0x60000000
986 * - 8 bit port size
987 * - Data errors checking is disabled
988 * - Read and write access
989 * - GPCM 60x bus
990 * - Access are handled by the memory controller according to MSEL
991 * - Not used for atomic operations
992 * - No data pipelining is done
993 * - Valid
994 */
995# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
996 BRx_PS_8 |\
997 BRx_MS_GPCM_P |\
998 BRx_V)
999
1000/* OR6 is configured as follows:
1001 *
1002 * - 2 MB
1003 * - *BCTL0 is asserted upon access to the current memory bank
1004 * - *CW / *WE are negated a quarter of a clock earlier
1005 * - *CS is output at the same time as the address lines
1006 * - Uses a clock cycle length of 5
1007 * - *PSDVAL is generated internally by the memory controller
1008 * unless *GTA is asserted earlier externally.
1009 * - Relaxed timing is generated by the GPCM for accesses
1010 * initiated to this memory region.
1011 * - One idle clock is inserted between a read access from the
1012 * current bank and the next access.
1013 */
1014# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
1015 ORxG_CSNT |\
1016 ORxG_ACS_DIV1 |\
1017 ORxG_SCY_5_CLK |\
1018 ORxG_TRLX |\
1019 ORxG_EHTR)
1020#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
1021
1022/*-----------------------------------------------------------------------
1023 * BR7 - Base Register
1024 * Ref: Section 10.3.1 on page 10-14
1025 * OR7 - Option Register
1026 * Ref: Section 10.3.2 on page 10-18
1027 *-----------------------------------------------------------------------
1028 */
1029
1030/* Bank 7 - LEDs and switches
1031 *
1032 * LEDs are at 0x00001 (write only)
1033 * switches are at 0x00001 (read only)
1034 */
1035#ifdef CFG_LED_BASE
1036
1037/* BR7 is configured as follows:
1038 *
1039 * - Base address of 0xA0000000
1040 * - 8 bit port size
1041 * - Data errors checking is disabled
1042 * - Read and write access
1043 * - GPCM 60x bus
1044 * - Access are handled by the memory controller according to MSEL
1045 * - Not used for atomic operations
1046 * - No data pipelining is done
1047 * - Valid
1048 */
1049# define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK) |\
1050 BRx_PS_8 |\
1051 BRx_MS_GPCM_P |\
1052 BRx_V)
1053
1054/* OR7 is configured as follows:
1055 *
1056 * - 1 byte
1057 * - *BCTL0 is asserted upon access to the current memory bank
1058 * - *CW / *WE are negated a quarter of a clock earlier
1059 * - *CS is output at the same time as the address lines
1060 * - Uses a clock cycle length of 15
1061 * - *PSDVAL is generated internally by the memory controller
1062 * unless *GTA is asserted earlier externally.
1063 * - Relaxed timing is generated by the GPCM for accesses
1064 * initiated to this memory region.
1065 * - One idle clock is inserted between a read access from the
1066 * current bank and the next access.
1067 */
1068# define CFG_OR7_PRELIM (ORxG_AM_MSK |\
1069 ORxG_CSNT |\
1070 ORxG_ACS_DIV1 |\
1071 ORxG_SCY_15_CLK |\
1072 ORxG_TRLX |\
1073 ORxG_EHTR)
1074#endif /* CFG_LED_BASE */
1075
wdenkfe8c2802002-11-03 00:38:21 +00001076/*
1077 * Internal Definitions
1078 *
1079 * Boot Flags
1080 */
wdenk10a36a92004-07-10 23:02:23 +00001081#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1082#define BOOTFLAG_WARM 0x02 /* Software reboot */
wdenkfe8c2802002-11-03 00:38:21 +00001083
1084#endif /* __CONFIG_H */