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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / c8a6bade5b558beadb0547fa4571b71d1ecbf954 / . / arch / riscv / cpu / nx25 / start.S
blob: 6a076639d34191f9f423a66062c64b78c5551842 [file] [log] [blame]
Rick Chene8e39592017-12-26 13:55:48 +0800[diff] [blame]1/*
2 * Startup Code for RISC-V Core
3 *
4 * Copyright (c) 2017 Microsemi Corporation.
5 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
6 *
7 * Copyright (C) 2017 Andes Technology Corporation
8 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <asm-offsets.h>
14#include <config.h>
15#include <common.h>
16#include <elf.h>
17#include <asm/encoding.h>
18
19#ifdef CONFIG_32BIT
20#define LREG lw
21#define SREG sw
22#define REGBYTES 4
23#define RELOC_TYPE R_RISCV_32
24#define SYM_INDEX 0x8
25#define SYM_SIZE 0x10
26#else
27#define LREG ld
28#define SREG sd
29#define REGBYTES 8
30#define RELOC_TYPE R_RISCV_64
31#define SYM_INDEX 0x20
32#define SYM_SIZE 0x18
33#endif
34
35.section .text
36.globl _start
37_start:
38 j handle_reset
39
40nmi_vector:
41 j nmi_vector
42
43trap_vector:
44 j trap_entry
45
46.global trap_entry
47handle_reset:
48 la t0, trap_entry
49 csrw mtvec, t0
50 csrwi mstatus, 0
51 csrwi mie, 0
52
53/*
54 * Do CPU critical regs init only at reboot,
55 * not when booting from ram
56 */
57#ifdef CONFIG_INIT_CRITICAL
58 jal cpu_init_crit /* Do CPU critical regs init */
59#endif
60
61/*
62 * Set stackpointer in internal/ex RAM to call board_init_f
63 */
64call_board_init_f:
65 li t0, -16
66 li t1, CONFIG_SYS_INIT_SP_ADDR
67 and sp, t1, t0 /* force 16 byte alignment */
68
69#ifdef CONFIG_DEBUG_UART
70 jal debug_uart_init
71#endif
72
73call_board_init_f_0:
74 mv a0, sp
75 jal board_init_f_alloc_reserve
76 mv sp, a0
77 jal board_init_f_init_reserve
78
79 mv a0, zero /* a0 <-- boot_flags = 0 */
80 la t5, board_init_f
81 jr t5 /* jump to board_init_f() */
82
83/*
84 * void relocate_code (addr_sp, gd, addr_moni)
85 *
86 * This "function" does not return, instead it continues in RAM
87 * after relocating the monitor code.
88 *
89 */
90.globl relocate_code
91relocate_code:
92 mv s2, a0 /* save addr_sp */
93 mv s3, a1 /* save addr of gd */
94 mv s4, a2 /* save addr of destination */
95
96/*
97 *Set up the stack
98 */
99stack_setup:
100 mv sp, s2
101 la t0, _start
102 sub t6, s4, t0 /* t6 <- relocation offset */
103 beq t0, s4, clear_bss /* skip relocation */
104
105 mv t1, s4 /* t1 <- scratch for copy_loop */
106 la t3, __bss_start
107 sub t3, t3, t0 /* t3 <- __bss_start_ofs */
108 add t2, t0, t3 /* t2 <- source end address */
109
110copy_loop:
111 LREG t5, 0(t0)
112 addi t0, t0, REGBYTES
113 SREG t5, 0(t1)
114 addi t1, t1, REGBYTES
115 blt t0, t2, copy_loop
116
117/*
118 * Update dynamic relocations after board_init_f
119 */
120fix_rela_dyn:
121 la t1, __rel_dyn_start
122 la t2, __rel_dyn_end
123 beq t1, t2, clear_bss
124 add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
125 add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
126
127/*
128 * skip first reserved entry: address, type, addend
129 */
130 bne t1, t2, 7f
131
1326:
133 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
134 li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
135 bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
136 LREG t3, -(REGBYTES*3)(t1)
137 LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
138 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
139 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
140 SREG t5, 0(t3)
1417:
142 addi t1, t1, (REGBYTES*3)
143 ble t1, t2, 6b
144
1458:
146 la t4, __dyn_sym_start
147 add t4, t4, t6
148
1499:
150 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
151 srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
152 andi t5, t5, 0xFF /* t5 <--- relocation type */
153 li t3, RELOC_TYPE
154 bne t5, t3, 10f /* skip non-addned entries */
155
156 LREG t3, -(REGBYTES*3)(t1)
157 li t5, SYM_SIZE
158 mul t0, t0, t5
159 add s1, t4, t0
160 LREG t5, REGBYTES(s1)
161 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
162 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
163 SREG t5, 0(t3)
16410:
165 addi t1, t1, (REGBYTES*3)
166 ble t1, t2, 9b
167
168/*
169 * trap update
170*/
171 la t0, trap_entry
172 add t0, t0, t6
173 csrw mtvec, t0
174
175clear_bss:
176 la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
177 add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
178 la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
179 add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
180 li t2, 0x00000000 /* clear */
181 beq t0, t1, call_board_init_r
182
183clbss_l:
184 SREG t2, 0(t0) /* clear loop... */
185 addi t0, t0, REGBYTES
186 bne t0, t1, clbss_l
187
188/*
189 * We are done. Do not return, instead branch to second part of board
190 * initialization, now running from RAM.
191 */
192call_board_init_r:
193 la t0, board_init_r
194 mv t4, t0 /* offset of board_init_r() */
195 add t4, t4, t6 /* real address of board_init_r() */
196/*
197 * setup parameters for board_init_r
198 */
199 mv a0, s3 /* gd_t */
200 mv a1, s4 /* dest_addr */
201
202/*
203 * jump to it ...
204 */
205 jr t4 /* jump to board_init_r() */
206
207/*
208 * trap entry
209 */
210trap_entry:
211 addi sp, sp, -32*REGBYTES
212 SREG x1, 1*REGBYTES(sp)
213 SREG x2, 2*REGBYTES(sp)
214 SREG x3, 3*REGBYTES(sp)
215 SREG x4, 4*REGBYTES(sp)
216 SREG x5, 5*REGBYTES(sp)
217 SREG x6, 6*REGBYTES(sp)
218 SREG x7, 7*REGBYTES(sp)
219 SREG x8, 8*REGBYTES(sp)
220 SREG x9, 9*REGBYTES(sp)
221 SREG x10, 10*REGBYTES(sp)
222 SREG x11, 11*REGBYTES(sp)
223 SREG x12, 12*REGBYTES(sp)
224 SREG x13, 13*REGBYTES(sp)
225 SREG x14, 14*REGBYTES(sp)
226 SREG x15, 15*REGBYTES(sp)
227 SREG x16, 16*REGBYTES(sp)
228 SREG x17, 17*REGBYTES(sp)
229 SREG x18, 18*REGBYTES(sp)
230 SREG x19, 19*REGBYTES(sp)
231 SREG x20, 20*REGBYTES(sp)
232 SREG x21, 21*REGBYTES(sp)
233 SREG x22, 22*REGBYTES(sp)
234 SREG x23, 23*REGBYTES(sp)
235 SREG x24, 24*REGBYTES(sp)
236 SREG x25, 25*REGBYTES(sp)
237 SREG x26, 26*REGBYTES(sp)
238 SREG x27, 27*REGBYTES(sp)
239 SREG x28, 28*REGBYTES(sp)
240 SREG x29, 29*REGBYTES(sp)
241 SREG x30, 30*REGBYTES(sp)
242 SREG x31, 31*REGBYTES(sp)
243 csrr a0, mcause
244 csrr a1, mepc
245 mv a2, sp
246 jal handle_trap
247 csrw mepc, a0
248
249/*
250 * Remain in M-mode after mret
251 */
252 li t0, MSTATUS_MPP
253 csrs mstatus, t0
254 LREG x1, 1*REGBYTES(sp)
255 LREG x2, 2*REGBYTES(sp)
256 LREG x3, 3*REGBYTES(sp)
257 LREG x4, 4*REGBYTES(sp)
258 LREG x5, 5*REGBYTES(sp)
259 LREG x6, 6*REGBYTES(sp)
260 LREG x7, 7*REGBYTES(sp)
261 LREG x8, 8*REGBYTES(sp)
262 LREG x9, 9*REGBYTES(sp)
263 LREG x10, 10*REGBYTES(sp)
264 LREG x11, 11*REGBYTES(sp)
265 LREG x12, 12*REGBYTES(sp)
266 LREG x13, 13*REGBYTES(sp)
267 LREG x14, 14*REGBYTES(sp)
268 LREG x15, 15*REGBYTES(sp)
269 LREG x16, 16*REGBYTES(sp)
270 LREG x17, 17*REGBYTES(sp)
271 LREG x18, 18*REGBYTES(sp)
272 LREG x19, 19*REGBYTES(sp)
273 LREG x20, 20*REGBYTES(sp)
274 LREG x21, 21*REGBYTES(sp)
275 LREG x22, 22*REGBYTES(sp)
276 LREG x23, 23*REGBYTES(sp)
277 LREG x24, 24*REGBYTES(sp)
278 LREG x25, 25*REGBYTES(sp)
279 LREG x26, 26*REGBYTES(sp)
280 LREG x27, 27*REGBYTES(sp)
281 LREG x28, 28*REGBYTES(sp)
282 LREG x29, 29*REGBYTES(sp)
283 LREG x30, 30*REGBYTES(sp)
284 LREG x31, 31*REGBYTES(sp)
285 addi sp, sp, 32*REGBYTES
286 mret
287
288#ifdef CONFIG_INIT_CRITICAL
289cpu_init_crit:
290 ret
291#endif