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Nagabhushana Netagunte06194b62011-11-09 16:53:33 -05001/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Based on davinci_dvevm.h. Original Copyrights follow:
5 *
6 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/*
27 * Board
28 */
29#define CONFIG_DRIVER_TI_EMAC
30#define CONFIG_USE_SPIFLASH
31
32
33/*
34 * SoC Configuration
35 */
36#define CONFIG_MACH_DAVINCI_DA850_EVM
37#define CONFIG_ARM926EJS /* arm926ejs CPU core */
38#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
Christian Riesch52b0f872011-11-28 23:46:18 +000039#define CONFIG_SOC_DA850 /* TI DA850 SoC */
Nagabhushana Netagunte06194b62011-11-09 16:53:33 -050040#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
41#define CONFIG_SYS_OSCIN_FREQ 24000000
42#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
43#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
44#define CONFIG_SYS_HZ 1000
45#define CONFIG_SKIP_LOWLEVEL_INIT
46#define CONFIG_SYS_TEXT_BASE 0xc1080000
Manjunath Hadli754f8cb2011-10-10 21:06:38 +000047#define CONFIG_DA850_AM18X_EVM
Nagabhushana Netagunte06194b62011-11-09 16:53:33 -050048/*
49 * Memory Info
50 */
51#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
52#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
53#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
54#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
55
56/* memtest start addr */
57#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
58
59/* memtest will be run on 16MB */
60#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
61
62#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
63#define CONFIG_STACKSIZE (256*1024) /* regular stack */
64
65/*
66 * Serial Driver info
67 */
68#define CONFIG_SYS_NS16550
69#define CONFIG_SYS_NS16550_SERIAL
70#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
71#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
72#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
73#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
74#define CONFIG_BAUDRATE 115200 /* Default baud rate */
75#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
76
77#define CONFIG_SPI
78#define CONFIG_SPI_FLASH
79#define CONFIG_SPI_FLASH_WINBOND
80#define CONFIG_DAVINCI_SPI
81#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
82#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
83#define CONFIG_SF_DEFAULT_SPEED 30000000
84#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
85
86/*
87 * I2C Configuration
88 */
89#define CONFIG_HARD_I2C
90#define CONFIG_DRIVER_DAVINCI_I2C
91#define CONFIG_SYS_I2C_SPEED 25000
92#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
93#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
94
95/*
96 * Flash & Environment
97 */
98#ifdef CONFIG_USE_NAND
99#undef CONFIG_ENV_IS_IN_FLASH
100#define CONFIG_NAND_DAVINCI
101#define CONFIG_SYS_NO_FLASH
102#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
103#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
104#define CONFIG_ENV_SIZE (128 << 10)
105#define CONFIG_SYS_NAND_USE_FLASH_BBT
106#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
107#define CONFIG_SYS_NAND_PAGE_2K
108#define CONFIG_SYS_NAND_CS 3
109#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
110#define CONFIG_SYS_CLE_MASK 0x10
111#define CONFIG_SYS_ALE_MASK 0x8
112#undef CONFIG_SYS_NAND_HW_ECC
113#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
114#define NAND_MAX_CHIPS 1
115#endif
116
117/*
118 * Network & Ethernet Configuration
119 */
120#ifdef CONFIG_DRIVER_TI_EMAC
121#define CONFIG_EMAC_MDIO_PHY_NUM 0
122#define CONFIG_MII
123#define CONFIG_BOOTP_DEFAULT
124#define CONFIG_BOOTP_DNS
125#define CONFIG_BOOTP_DNS2
126#define CONFIG_BOOTP_SEND_HOSTNAME
127#define CONFIG_NET_RETRY_COUNT 10
128#define CONFIG_NET_MULTI
129#endif
130
131#ifdef CONFIG_USE_NOR
132#define CONFIG_ENV_IS_IN_FLASH
133#define CONFIG_FLASH_CFI_DRIVER
134#define CONFIG_SYS_FLASH_CFI
135#define CONFIG_SYS_FLASH_PROTECTION
136#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
137#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
138#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
139#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
140#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
141#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
142#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
143 + 3)
144#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
145#endif
146
147#ifdef CONFIG_USE_SPIFLASH
148#undef CONFIG_ENV_IS_IN_FLASH
149#undef CONFIG_ENV_IS_IN_NAND
150#define CONFIG_ENV_IS_IN_SPI_FLASH
151#define CONFIG_ENV_SIZE (64 << 10)
152#define CONFIG_ENV_OFFSET (256 << 10)
153#define CONFIG_ENV_SECT_SIZE (64 << 10)
154#define CONFIG_SYS_NO_FLASH
155#endif
156
157/*
158 * U-Boot general configuration
159 */
160#define CONFIG_MISC_INIT_R
161#define CONFIG_BOOTFILE "uImage" /* Boot file name */
162#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
163#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
164#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
165#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
166#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
167#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
168#define CONFIG_VERSION_VARIABLE
169#define CONFIG_AUTO_COMPLETE
170#define CONFIG_SYS_HUSH_PARSER
171#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
172#define CONFIG_CMDLINE_EDITING
173#define CONFIG_SYS_LONGHELP
174#define CONFIG_CRC32_VERIFY
175#define CONFIG_MX_CYCLIC
176
177/*
178 * Linux Information
179 */
180#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
181#define CONFIG_HWCONFIG /* enable hwconfig */
182#define CONFIG_CMDLINE_TAG
183#define CONFIG_REVISION_TAG
184#define CONFIG_SETUP_MEMORY_TAGS
185#define CONFIG_BOOTARGS \
186 "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
187#define CONFIG_BOOTDELAY 3
188#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
189
190/*
191 * U-Boot commands
192 */
193#include <config_cmd_default.h>
194#define CONFIG_CMD_ENV
195#define CONFIG_CMD_ASKENV
196#define CONFIG_CMD_DHCP
197#define CONFIG_CMD_DIAG
198#define CONFIG_CMD_MII
199#define CONFIG_CMD_PING
200#define CONFIG_CMD_SAVES
201#define CONFIG_CMD_MEMORY
202
203#ifndef CONFIG_DRIVER_TI_EMAC
204#undef CONFIG_CMD_NET
205#undef CONFIG_CMD_DHCP
206#undef CONFIG_CMD_MII
207#undef CONFIG_CMD_PING
208#endif
209
210#ifdef CONFIG_USE_NAND
211#undef CONFIG_CMD_FLASH
212#undef CONFIG_CMD_IMLS
213#define CONFIG_CMD_NAND
214
215#define CONFIG_CMD_MTDPARTS
216#define CONFIG_MTD_DEVICE
217#define CONFIG_MTD_PARTITIONS
218#define CONFIG_LZO
219#define CONFIG_RBTREE
220#define CONFIG_CMD_UBI
221#define CONFIG_CMD_UBIFS
222#endif
223
224#ifdef CONFIG_USE_SPIFLASH
225#undef CONFIG_CMD_IMLS
226#undef CONFIG_CMD_FLASH
227#define CONFIG_CMD_SPI
228#define CONFIG_CMD_SF
229#define CONFIG_CMD_SAVEENV
230#endif
231
232#if !defined(CONFIG_USE_NAND) && \
233 !defined(CONFIG_USE_NOR) && \
234 !defined(CONFIG_USE_SPIFLASH)
235#define CONFIG_ENV_IS_NOWHERE
236#define CONFIG_SYS_NO_FLASH
237#define CONFIG_ENV_SIZE (16 << 10)
238#undef CONFIG_CMD_IMLS
239#undef CONFIG_CMD_ENV
240#endif
241
242/* additions for new relocation code, must added to all boards */
243#define CONFIG_SYS_SDRAM_BASE 0xc0000000
244#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
245 /* Fix this */ GENERATED_GBL_DATA_SIZE)
246#endif /* __CONFIG_H */