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Dave Liu5f820432006-11-03 19:33:44 -06001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Dave Liu5f820432006-11-03 19:33:44 -060014 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
Dave Liu5f820432006-11-03 19:33:44 -060025/*
26 * High Level Configuration Options
27 */
28#define CONFIG_E300 1 /* E300 family */
29#define CONFIG_QE 1 /* Has QE */
30#define CONFIG_MPC83XX 1 /* MPC83XX family */
31#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
32#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
Tony Li14778582007-08-17 10:35:59 +080033#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
34#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
Dave Liu5f820432006-11-03 19:33:44 -060035
36/*
37 * System Clock Setup
38 */
39#ifdef CONFIG_PCISLAVE
40#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
41#else
42#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
43#endif
44
45#ifndef CONFIG_SYS_CLK_FREQ
46#define CONFIG_SYS_CLK_FREQ 66000000
47#endif
48
49/*
50 * Hardware Reset Configuration Word
51 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_HRCW_LOW (\
Dave Liu5f820432006-11-03 19:33:44 -060053 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
54 HRCWL_DDR_TO_SCB_CLK_1X1 |\
55 HRCWL_CSB_TO_CLKIN_4X1 |\
56 HRCWL_VCO_1X2 |\
57 HRCWL_CE_PLL_VCO_DIV_4 |\
58 HRCWL_CE_PLL_DIV_1X1 |\
59 HRCWL_CE_TO_PLL_1X6 |\
60 HRCWL_CORE_TO_CSB_2X1)
61
62#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu5f820432006-11-03 19:33:44 -060064 HRCWH_PCI_AGENT |\
65 HRCWH_PCI1_ARBITER_DISABLE |\
66 HRCWH_PCICKDRV_DISABLE |\
67 HRCWH_CORE_ENABLE |\
68 HRCWH_FROM_0XFFF00100 |\
69 HRCWH_BOOTSEQ_DISABLE |\
70 HRCWH_SW_WATCHDOG_DISABLE |\
71 HRCWH_ROM_LOC_LOCAL_16BIT)
72#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu5f820432006-11-03 19:33:44 -060074 HRCWH_PCI_HOST |\
75 HRCWH_PCI1_ARBITER_ENABLE |\
76 HRCWH_PCICKDRV_ENABLE |\
77 HRCWH_CORE_ENABLE |\
78 HRCWH_FROM_0X00000100 |\
79 HRCWH_BOOTSEQ_DISABLE |\
80 HRCWH_SW_WATCHDOG_DISABLE |\
81 HRCWH_ROM_LOC_LOCAL_16BIT)
82#endif
83
84/*
85 * System IO Config
86 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_SICRH 0x00000000
88#define CONFIG_SYS_SICRL 0x40000000
Dave Liu5f820432006-11-03 19:33:44 -060089
90#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
Tony Li14778582007-08-17 10:35:59 +080091#define CONFIG_BOARD_EARLY_INIT_R
Dave Liu5f820432006-11-03 19:33:44 -060092
93/*
94 * IMMR new address
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu5f820432006-11-03 19:33:44 -060097
98/*
99 * DDR Setup
100 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
102#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400103#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
105#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Xie Xiaobob110f402007-02-14 18:27:06 +0800106 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Dave Liu5f820432006-11-03 19:33:44 -0600107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_83XX_DDR_USES_CS0
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600109
Xie Xiaobob110f402007-02-14 18:27:06 +0800110#define CONFIG_DDR_ECC /* support DDR ECC function */
Dave Liu5f820432006-11-03 19:33:44 -0600111#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
112
Xie Xiaobob110f402007-02-14 18:27:06 +0800113/*
114 * DDRCDR - DDR Control Driver Register
115 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
Xie Xiaobob110f402007-02-14 18:27:06 +0800117
Dave Liu5f820432006-11-03 19:33:44 -0600118#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
119#if defined(CONFIG_SPD_EEPROM)
120/*
121 * Determine DDR configuration from I2C interface.
122 */
123#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
124#else
125/*
126 * Manually set up DDR parameters
127 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Xie Xiaobob110f402007-02-14 18:27:06 +0800129#if defined(CONFIG_DDR_II)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_DDRCDR 0x80080001
131#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
132#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
133#define CONFIG_SYS_DDR_TIMING_0 0x00220802
134#define CONFIG_SYS_DDR_TIMING_1 0x38357322
135#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
136#define CONFIG_SYS_DDR_TIMING_3 0x00000000
137#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
138#define CONFIG_SYS_DDR_MODE 0x47d00432
139#define CONFIG_SYS_DDR_MODE2 0x8000c000
140#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
141#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
142#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Xie Xiaobob110f402007-02-14 18:27:06 +0800143#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
145#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
146#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
147#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
148#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
149#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
Dave Liu5f820432006-11-03 19:33:44 -0600150#endif
Xie Xiaobob110f402007-02-14 18:27:06 +0800151#endif
Dave Liu5f820432006-11-03 19:33:44 -0600152
153/*
154 * Memory test
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
157#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
158#define CONFIG_SYS_MEMTEST_END 0x00100000
Dave Liu5f820432006-11-03 19:33:44 -0600159
160/*
161 * The reserved memory
162 */
163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Dave Liu5f820432006-11-03 19:33:44 -0600165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
167#define CONFIG_SYS_RAMBOOT
Dave Liu5f820432006-11-03 19:33:44 -0600168#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#undef CONFIG_SYS_RAMBOOT
Dave Liu5f820432006-11-03 19:33:44 -0600170#endif
171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
173#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
174#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Dave Liu5f820432006-11-03 19:33:44 -0600175
176/*
177 * Initial RAM Base Address Setup
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_INIT_RAM_LOCK 1
180#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
181#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
182#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
183#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
Dave Liu5f820432006-11-03 19:33:44 -0600184
185/*
186 * Local Bus Configuration & Clock Setup
187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
189#define CONFIG_SYS_LBC_LBCR 0x00000000
Dave Liu5f820432006-11-03 19:33:44 -0600190
191/*
192 * FLASH on the Local Bus
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200195#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
197#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
198#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Jerry Van Baren82e45a22008-03-18 21:44:41 -0400199#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Dave Liu5f820432006-11-03 19:33:44 -0600200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
202#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
Dave Liu5f820432006-11-03 19:33:44 -0600203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
Dave Liu5f820432006-11-03 19:33:44 -0600205 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
206 BR_V) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400208 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
Xie Xiaobob110f402007-02-14 18:27:06 +0800209 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
Dave Liu5f820432006-11-03 19:33:44 -0600210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
212#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Dave Liu5f820432006-11-03 19:33:44 -0600213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#undef CONFIG_SYS_FLASH_CHECKSUM
Dave Liu5f820432006-11-03 19:33:44 -0600215
216/*
217 * BCSR on the Local Bus
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_BCSR 0xF8000000
220#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
221#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
Dave Liu5f820432006-11-03 19:33:44 -0600222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
224#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
Dave Liu5f820432006-11-03 19:33:44 -0600225
226/*
227 * SDRAM on the Local Bus
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
230#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Dave Liu5f820432006-11-03 19:33:44 -0600231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */
Dave Liu5f820432006-11-03 19:33:44 -0600233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#ifdef CONFIG_SYS_LB_SDRAM
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400235#define CONFIG_SYS_LBLAWBAR2 0
236#define CONFIG_SYS_LBLAWAR2 0x80000019 /* 64MB */
Dave Liu5f820432006-11-03 19:33:44 -0600237
238/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
239/*
240 * Base Register 2 and Option Register 2 configure SDRAM.
Dave Liu5f820432006-11-03 19:33:44 -0600241 *
242 * For BR2, need:
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400243 * Base address = BR[0:16] = dynamic
Dave Liu5f820432006-11-03 19:33:44 -0600244 * port size = 32-bits = BR2[19:20] = 11
245 * no parity checking = BR2[21:22] = 00
246 * SDRAM for MSEL = BR2[24:26] = 011
247 * Valid = BR[31] = 1
248 *
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100249 * 0 4 8 12 16 20 24 28
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400250 * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
Dave Liu5f820432006-11-03 19:33:44 -0600251 */
252
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400253#define CONFIG_SYS_BR2 0x00001861 /*Port size=32bit, MSEL=SDRAM */
Dave Liu5f820432006-11-03 19:33:44 -0600254
255/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Dave Liu5f820432006-11-03 19:33:44 -0600257 *
258 * For OR2, need:
259 * 64MB mask for AM, OR2[0:7] = 1111 1100
260 * XAM, OR2[17:18] = 11
261 * 9 columns OR2[19-21] = 010
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100262 * 13 rows OR2[23-25] = 100
Dave Liu5f820432006-11-03 19:33:44 -0600263 * EAD set for extra time OR[31] = 1
264 *
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100265 * 0 4 8 12 16 20 24 28
Dave Liu5f820432006-11-03 19:33:44 -0600266 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
267 */
268
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400269#define CONFIG_SYS_OR2 0xfc006901
Dave Liu5f820432006-11-03 19:33:44 -0600270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
272#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
Dave Liu5f820432006-11-03 19:33:44 -0600273
274/*
275 * LSDMR masks
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
278#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
279#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
280#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
281#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
282#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
283#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
284#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
Dave Liu5f820432006-11-03 19:33:44 -0600285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
Dave Liu5f820432006-11-03 19:33:44 -0600287
288/*
289 * SDRAM Controller configuration sequence.
290 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_LBC_LSDMR_1 ( CONFIG_SYS_LBC_LSDMR_COMMON \
292 | CONFIG_SYS_LBC_LSDMR_OP_PCHALL)
293#define CONFIG_SYS_LBC_LSDMR_2 ( CONFIG_SYS_LBC_LSDMR_COMMON \
294 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
295#define CONFIG_SYS_LBC_LSDMR_3 ( CONFIG_SYS_LBC_LSDMR_COMMON \
296 | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
297#define CONFIG_SYS_LBC_LSDMR_4 ( CONFIG_SYS_LBC_LSDMR_COMMON \
298 | CONFIG_SYS_LBC_LSDMR_OP_MRW)
299#define CONFIG_SYS_LBC_LSDMR_5 ( CONFIG_SYS_LBC_LSDMR_COMMON \
300 | CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
Dave Liu5f820432006-11-03 19:33:44 -0600301
302#endif
303
304/*
305 * Windows to access PIB via local bus
306 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */
308#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */
Dave Liu5f820432006-11-03 19:33:44 -0600309
310/*
311 * CS4 on Local Bus, to PIB
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
314#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
Dave Liu5f820432006-11-03 19:33:44 -0600315
316/*
317 * CS5 on Local Bus, to PIB
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
320#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
Dave Liu5f820432006-11-03 19:33:44 -0600321
322/*
323 * Serial Port
324 */
325#define CONFIG_CONS_INDEX 1
326#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_NS16550
328#define CONFIG_SYS_NS16550_SERIAL
329#define CONFIG_SYS_NS16550_REG_SIZE 1
330#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu5f820432006-11-03 19:33:44 -0600331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_BAUDRATE_TABLE \
Dave Liu5f820432006-11-03 19:33:44 -0600333 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
336#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu5f820432006-11-03 19:33:44 -0600337
Kim Phillips22d71a72007-02-27 18:41:08 -0600338#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Dave Liu5f820432006-11-03 19:33:44 -0600339/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_HUSH_PARSER
341#ifdef CONFIG_SYS_HUSH_PARSER
342#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Dave Liu5f820432006-11-03 19:33:44 -0600343#endif
344
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600345/* pass open firmware flat tree */
Gerald Van Baren213bf8c2007-03-31 12:23:51 -0400346#define CONFIG_OF_LIBFDT 1
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600347#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600348#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600349
Dave Liu5f820432006-11-03 19:33:44 -0600350/* I2C */
351#define CONFIG_HARD_I2C /* I2C with hardware support */
352#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Timur Tabibe5e6182006-11-03 19:15:00 -0600353#define CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
355#define CONFIG_SYS_I2C_SLAVE 0x7F
356#define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
357#define CONFIG_SYS_I2C_OFFSET 0x3000
358#define CONFIG_SYS_I2C2_OFFSET 0x3100
Dave Liu5f820432006-11-03 19:33:44 -0600359
360/*
361 * Config on-board RTC
362 */
363#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu5f820432006-11-03 19:33:44 -0600365
366/*
367 * General PCI
368 * Addresses are mapped 1-1.
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
371#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
372#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
373#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
374#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
375#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
376#define CONFIG_SYS_PCI_IO_BASE 0x00000000
377#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
378#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu5f820432006-11-03 19:33:44 -0600379
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
381#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
382#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu5f820432006-11-03 19:33:44 -0600383
384
385#ifdef CONFIG_PCI
386
387#define CONFIG_NET_MULTI
388#define CONFIG_PCI_PNP /* do pci plug-and-play */
389
390#undef CONFIG_EEPRO100
391#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu5f820432006-11-03 19:33:44 -0600393
394#endif /* CONFIG_PCI */
395
396
397#ifndef CONFIG_NET_MULTI
398#define CONFIG_NET_MULTI 1
399#endif
400
401/*
Dave Liu7737d5c2006-11-03 12:11:15 -0600402 * QE UEC ethernet configuration
403 */
404#define CONFIG_UEC_ETH
Kim Phillips711a7942008-01-15 14:05:14 -0600405#define CONFIG_ETHPRIME "FSL UEC0"
Dave Liu7737d5c2006-11-03 12:11:15 -0600406#define CONFIG_PHY_MODE_NEED_CHANGE
407
408#define CONFIG_UEC_ETH1 /* GETH1 */
409
410#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
412#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
413#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
414#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
415#define CONFIG_SYS_UEC1_PHY_ADDR 0
416#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_GMII
Dave Liu7737d5c2006-11-03 12:11:15 -0600417#endif
418
419#define CONFIG_UEC_ETH2 /* GETH2 */
420
421#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
423#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
424#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
425#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
426#define CONFIG_SYS_UEC2_PHY_ADDR 1
427#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_GMII
Dave Liu7737d5c2006-11-03 12:11:15 -0600428#endif
429
430/*
Dave Liu5f820432006-11-03 19:33:44 -0600431 * Environment
432 */
433
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200435 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200437 #define CONFIG_ENV_SECT_SIZE 0x20000
438 #define CONFIG_ENV_SIZE 0x2000
Dave Liu5f820432006-11-03 19:33:44 -0600439#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200441 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200443 #define CONFIG_ENV_SIZE 0x2000
Dave Liu5f820432006-11-03 19:33:44 -0600444#endif
445
446#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu5f820432006-11-03 19:33:44 -0600448
Jon Loeliger8ea54992007-07-04 22:30:06 -0500449/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500450 * BOOTP options
451 */
452#define CONFIG_BOOTP_BOOTFILESIZE
453#define CONFIG_BOOTP_BOOTPATH
454#define CONFIG_BOOTP_GATEWAY
455#define CONFIG_BOOTP_HOSTNAME
456
457
458/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500459 * Command line configuration.
460 */
461#include <config_cmd_default.h>
462
463#define CONFIG_CMD_PING
464#define CONFIG_CMD_I2C
465#define CONFIG_CMD_ASKENV
Jerry Van Barenb5cdd7d2008-01-12 13:24:14 -0500466#define CONFIG_CMD_SDRAM
Jon Loeliger8ea54992007-07-04 22:30:06 -0500467
Dave Liu5f820432006-11-03 19:33:44 -0600468#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500469 #define CONFIG_CMD_PCI
Dave Liu5f820432006-11-03 19:33:44 -0600470#endif
471
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#if defined(CONFIG_SYS_RAMBOOT)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500473 #undef CONFIG_CMD_ENV
474 #undef CONFIG_CMD_LOADS
475#endif
476
Dave Liu5f820432006-11-03 19:33:44 -0600477
478#undef CONFIG_WATCHDOG /* watchdog disabled */
479
480/*
481 * Miscellaneous configurable options
482 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#define CONFIG_SYS_LONGHELP /* undef to save memory */
484#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
485#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Dave Liu5f820432006-11-03 19:33:44 -0600486
Jon Loeliger8ea54992007-07-04 22:30:06 -0500487#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu5f820432006-11-03 19:33:44 -0600489#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu5f820432006-11-03 19:33:44 -0600491#endif
492
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
494#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
495#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
496#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Dave Liu5f820432006-11-03 19:33:44 -0600497
498/*
499 * For booting Linux, the board info and command line data
500 * have to be in the first 8 MB of memory, since this is
501 * the maximum mapped by the Linux kernel during initialization.
502 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Dave Liu5f820432006-11-03 19:33:44 -0600504
505/*
506 * Core HID Setup
507 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_HID0_INIT 0x000000000
509#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
510#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu5f820432006-11-03 19:33:44 -0600511
512/*
Dave Liu5f820432006-11-03 19:33:44 -0600513 * MMU Setup
514 */
515
Becky Bruce31d82672008-05-08 19:02:12 -0500516#define CONFIG_HIGH_BATS 1 /* High BATs supported */
517
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400518/* DDR/LBC SDRAM: cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
520#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
521#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
522#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu5f820432006-11-03 19:33:44 -0600523
524/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200525#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
Dave Liu5f820432006-11-03 19:33:44 -0600526 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
528#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
529#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu5f820432006-11-03 19:33:44 -0600530
531/* BCSR: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_10 | \
Dave Liu5f820432006-11-03 19:33:44 -0600533 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
535#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
536#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu5f820432006-11-03 19:33:44 -0600537
538/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200539#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
540#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
541#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
Dave Liu5f820432006-11-03 19:33:44 -0600542 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu5f820432006-11-03 19:33:44 -0600544
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400545/* DDR/LBC SDRAM next 256M: cacheable */
546#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE)
547#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200548#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
549#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu5f820432006-11-03 19:33:44 -0600550
551/* Stack in dcache: cacheable, no memory coherence */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200552#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
553#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
554#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
555#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu5f820432006-11-03 19:33:44 -0600556
557#ifdef CONFIG_PCI
558/* PCI MEM space: cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200559#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
560#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
561#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
562#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu5f820432006-11-03 19:33:44 -0600563/* PCI MMIO space: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
Dave Liu5f820432006-11-03 19:33:44 -0600565 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200566#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
567#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
568#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu5f820432006-11-03 19:33:44 -0600569#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200570#define CONFIG_SYS_IBAT6L (0)
571#define CONFIG_SYS_IBAT6U (0)
572#define CONFIG_SYS_IBAT7L (0)
573#define CONFIG_SYS_IBAT7U (0)
574#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
575#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
576#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
577#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu5f820432006-11-03 19:33:44 -0600578#endif
579
580/*
581 * Internal Definitions
582 *
583 * Boot Flags
584 */
585#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
586#define BOOTFLAG_WARM 0x02 /* Software reboot */
587
Jon Loeliger8ea54992007-07-04 22:30:06 -0500588#if defined(CONFIG_CMD_KGDB)
Dave Liu5f820432006-11-03 19:33:44 -0600589#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
590#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
591#endif
592
593/*
594 * Environment Configuration
595 */
596
597#define CONFIG_ENV_OVERWRITE
598
599#if defined(CONFIG_UEC_ETH)
Kim Phillips977b5752008-01-09 15:24:06 -0600600#define CONFIG_HAS_ETH0
Dave Liu5f820432006-11-03 19:33:44 -0600601#define CONFIG_ETHADDR 00:04:9f:ef:01:01
602#define CONFIG_HAS_ETH1
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100603#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
Dave Liu5f820432006-11-03 19:33:44 -0600604#endif
605
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100606#define CONFIG_BAUDRATE 115200
Dave Liu5f820432006-11-03 19:33:44 -0600607
Kim Phillipsb2115752008-04-24 14:07:38 -0500608#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
Dave Liu5f820432006-11-03 19:33:44 -0600609
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100610#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
611#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Dave Liu5f820432006-11-03 19:33:44 -0600612
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100613#define CONFIG_EXTRA_ENV_SETTINGS \
614 "netdev=eth0\0" \
615 "consoledev=ttyS0\0" \
616 "ramdiskaddr=1000000\0" \
Dave Liu5f820432006-11-03 19:33:44 -0600617 "ramdiskfile=ramfs.83xx\0" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600618 "fdtaddr=400000\0" \
Kim Phillips270fe262008-03-07 12:27:31 -0600619 "fdtfile=mpc836x_mds.dtb\0" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600620 ""
Dave Liu5f820432006-11-03 19:33:44 -0600621
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100622#define CONFIG_NFSBOOTCOMMAND \
623 "setenv bootargs root=/dev/nfs rw " \
624 "nfsroot=$serverip:$rootpath " \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600625 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100626 "console=$consoledev,$baudrate $othbootargs;" \
627 "tftp $loadaddr $bootfile;" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600628 "tftp $fdtaddr $fdtfile;" \
629 "bootm $loadaddr - $fdtaddr"
Dave Liu5f820432006-11-03 19:33:44 -0600630
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600631#define CONFIG_RAMBOOTCOMMAND \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100632 "setenv bootargs root=/dev/ram rw " \
633 "console=$consoledev,$baudrate $othbootargs;" \
634 "tftp $ramdiskaddr $ramdiskfile;" \
635 "tftp $loadaddr $bootfile;" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600636 "tftp $fdtaddr $fdtfile;" \
637 "bootm $loadaddr $ramdiskaddr $fdtaddr"
638
Dave Liu5f820432006-11-03 19:33:44 -0600639
640#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
641
642#endif /* __CONFIG_H */