| wdenk | c935d3b | 2004-01-03 19:43:48 +0000 | [diff] [blame^] | 1 | |
| 2 | =============================================================================== |
| 3 | C P U , M E M O R Y , I N / O U T C O M P O N E N T S |
| 4 | =============================================================================== |
| 5 | see also [1]-[4] |
| 6 | |
| 7 | CPU: "standard_32" |
| 8 | 32 bit NIOS for 33.333 MHz (nasys_clock_freq = 33333000) |
| 9 | 256 Byte for register file (15 levels) |
| 10 | no instruction cache |
| 11 | no data cache |
| 12 | 1 KByte On Chip ROM with GERMS boot monitor |
| 13 | no On Chip RAM |
| 14 | MSTEP multiplier |
| 15 | no Debug Core |
| 16 | no On Chip Instrumentation (OCI) enabled |
| 17 | |
| 18 | U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000 |
| 19 | CFG_NIOS_CPU_ICACHE = 0 |
| 20 | CFG_NIOS_CPU_DCACHE = 0 |
| 21 | CFG_NIOS_CPU_REG_NUMS = 256 |
| 22 | CFG_NIOS_CPU_MUL = 0 |
| 23 | CFG_NIOS_CPU_MSTEP = 1 |
| 24 | CFG_NIOS_CPU_DBG_CORE = 0 |
| 25 | |
| 26 | IRQ: Nr. | used by |
| 27 | ------+-------------------------------------------------------- |
| 28 | 25 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 25 |
| 29 | 26 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 26 |
| 30 | 27 | PIO2 | CFG_NIOS_CPU_PIO2_IRQ = 27 |
| 31 | 28 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 28 (debug) |
| 32 | |
| 33 | MEMORY: 1 MByte Flash |
| 34 | 256 KByte SRAM |
| 35 | (SDRAM with standard SODIMM only) |
| 36 | |
| 37 | Timer: TIMER0: high priority programmable timer (IRQ25) |
| 38 | |
| 39 | U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0 |
| 40 | |
| 41 | PIO: Nr. | description |
| 42 | ------+-------------------------------------------------------- |
| 43 | PIO0 | SEVENSEG: 16 outputs for user seven segment display |
| 44 | PIO1 | LED: 8 outputs for user LEDs |
| 45 | PIO2 | BUTTON: 4 inputs for user push buttons (IRQ27) |
| 46 | PIO3 | LCD: 11 in/outputs for ASCII LCD |
| 47 | |
| 48 | U-Boot CFG: CFG_NIOS_CPU_SEVENSEG_PIO = 0 |
| 49 | CFG_NIOS_CPU_LED_PIO = 1 |
| 50 | CFG_NIOS_CPU_BUTTON_PIO = 2 |
| 51 | CFG_NIOS_CPU_LCD_PIO = 3 |
| 52 | |
| 53 | UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, |
| 54 | without handshake RTS/CTS (IRQ26) |
| 55 | UART1: fixed baudrate of 115200, fixed protocol 8N1, |
| 56 | without handshake RTS/CTS (IRQ28) |
| 57 | |
| 58 | |
| 59 | =============================================================================== |
| 60 | M E M O R Y M A P |
| 61 | =============================================================================== |
| 62 | |
| 63 | - - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - - |
| 64 | |
| 65 | 0x00200000 ---15------------8|7-------------0- |
| 66 | | sector 18 | \ |
| 67 | + 0x0f0000 |- - - - - - - - - - - - - - - -| | |
| 68 | | : | | |
| 69 | Flash |- - - - : - - - -| | |
| 70 | | sector 5 : | | |
| 71 | + 0x020000 |- - - - - - - - -| | |
| 72 | | sector 4 (size = 0x10000) | | |
| 73 | + 0x010000 |- - - - - - - - - - - - - - - -| > CFG_NIOS_CPU_FLASH_SIZE |
| 74 | | sector 3 (size = 0x08000) | | = 0x00100000 |
| 75 | + 0x008000 |- - - - - - - - - - - - - - - -| | |
| 76 | | sector 2 (size = 0x02000) | | |
| 77 | + 0x006000 |- - - - - - - - - - - - - - - -| | |
| 78 | | sector 1 (size = 0x02000) | | |
| 79 | + 0x004000 |- - - - - - - - - - - - - - - -| | |
| 80 | | sector 0 (size = 0x04000) | / |
| 81 | 0x00100000 ---15------------8|7-------------0- CFG_NIOS_CPU_FLASH_BASE |
| 82 | | | |
| 83 | : gap : |
| 84 | | | |
| 85 | 0x00080000 ---32-----------16|15------------0- |
| 86 | 0x00080000 --+32-----------16|15------------0+ |
| 87 | | . | \ \ |
| 88 | | . | | | |
| 89 | | . | | > CFG_NIOS_CPU_VEC_SIZE |
| 90 | | . | | | = 0x00000100 |
| 91 | | . | | / |
| 92 | 0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE |
| 93 | 0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK |
| 94 | | . | | \ |
| 95 | | . | | | |
| 96 | | . | | > stack area |
| 97 | | . | | | |
| 98 | | . | | V |
| 99 | | . | | |
| 100 | SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE |
| 101 | | . | | = 0x00040000 |
| 102 | | | / |
| 103 | 0x00040000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE |
| 104 | | | |
| 105 | : gap : |
| 106 | : : |
| 107 | |
| 108 | - - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - - |
| 109 | |
| 110 | : : |
| 111 | : gap : |
| 112 | | | |
| 113 | 0x00000400 ---32-----------16|15------------0- |
| 114 | | (unused) | \ |
| 115 | + 0x1c |- - - - - - - - - - - - - - - -| | |
| 116 | | (unused) | | |
| 117 | + 0x18 |- - - - - - - - - - - - - - - -| | |
| 118 | | (unused) | | |
| 119 | + 0x14 |- - - - - - - - - - - - - - - -| | |
| 120 | UART0 | (unused) | > 0x00000020 |
| 121 | [2] + 0x10 |- - - - - - - - - - - - - - - -| | |
| 122 | | control (10 bit) (rw) | | |
| 123 | + 0x0c |- - - - - - - - - - - - - - - -| | |
| 124 | | status (10 bit) (rw) | | |
| 125 | + 0x08 |- - - - - - - - - - - - - - - -| | |
| 126 | | txdata (8 bit) (wo) | | |
| 127 | + 0x04 |- - - - - - - - - - - - - - - -| | |
| 128 | | rxdata (8 bit) (ro) | / |
| 129 | 0x000004c0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1 |
| 130 | | | |
| 131 | : gap : |
| 132 | | | |
| 133 | 0x00000490 ---32-----------16|15------------0- |
| 134 | | (unused) | \ |
| 135 | + 0x0c |- - - - - - - - - - - - - - - -| | |
| 136 | PIO3 | (unused) | | |
| 137 | [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 |
| 138 | | direction (11 bit) (rw) | | |
| 139 | + 0x04 |- - - - - - - - - - - - - - - -| | |
| 140 | | data (11 bit) (rw) | / |
| 141 | 0x00000480 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3 |
| 142 | | edgecapture (12 bit) (rw) | \ |
| 143 | + 0x0c |- - - - - - - - - - - - - - - -| | |
| 144 | PIO2 | interruptmask (12 bit) (rw) | | |
| 145 | [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 |
| 146 | | (unused) | | |
| 147 | + 0x04 |- - - - - - - - - - - - - - - -| | |
| 148 | | data (12 bit) (ro) | / |
| 149 | 0x00000470 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2 |
| 150 | | (unused) | \ |
| 151 | + 0x0c |- - - - - - - - - - - - - - - -| | |
| 152 | PIO1 | (unused) | | |
| 153 | [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 |
| 154 | | direction (2 bit) (rw) | | |
| 155 | + 0x04 |- - - - - - - - - - - - - - - -| | |
| 156 | | data (2 bit) (rw) | / |
| 157 | 0x00000460 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 |
| 158 | | (unused) | \ |
| 159 | + 0x1c |- - - - - - - - - - - - - - - -| | |
| 160 | | (unused) | | |
| 161 | + 0x18 |- - - - - - - - - - - - - - - -| | |
| 162 | | snaph (16 bit) (rw) | | |
| 163 | + 0x14 |- - - - - - - - - - - - - - - -| | |
| 164 | TIMER0 | snapl (16 bit) (rw) | | |
| 165 | [3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 |
| 166 | | periodh (16 bit) (rw) | | |
| 167 | + 0x0c |- - - - - - - - - - - - - - - -| | |
| 168 | | periodl (16 bit) (rw) | | |
| 169 | + 0x08 |- - - - - - - - - - - - - - - -| | |
| 170 | | control (4 bit) (rw) | | |
| 171 | + 0x04 |- - - - - - - - - - - - - - - -| | |
| 172 | | status (2 bit) (rw) | / |
| 173 | 0x00000440 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 |
| 174 | | (unused) | \ |
| 175 | + 0x0c |- - - - - - - - - - - - - - - -| | |
| 176 | PIO0 | (unused) | | |
| 177 | [4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 |
| 178 | | (unused) | | |
| 179 | + 0x04 |- - - - - - - - - - - - - - - -| | |
| 180 | | data (16 bit) (wo) | / |
| 181 | 0x00000420 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 |
| 182 | | (unused) | \ |
| 183 | + 0x1c |- - - - - - - - - - - - - - - -| | |
| 184 | | (unused) | | |
| 185 | + 0x18 |- - - - - - - - - - - - - - - -| | |
| 186 | | (unused) | | |
| 187 | + 0x14 |- - - - - - - - - - - - - - - -| | |
| 188 | UART0 | (unused) | > 0x00000020 |
| 189 | [2] + 0x10 |- - - - - - - - - - - - - - - -| | |
| 190 | | control (10 bit) (rw) | | |
| 191 | + 0x0c |- - - - - - - - - - - - - - - -| | |
| 192 | | status (10 bit) (rw) | | |
| 193 | + 0x08 |- - - - - - - - - - - - - - - -| | |
| 194 | | txdata (8 bit) (wo) | | |
| 195 | + 0x04 |- - - - - - - - - - - - - - - -| | |
| 196 | | rxdata (8 bit) (ro) | / |
| 197 | 0x00000400 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 |
| 198 | |
| 199 | - - - - - - - - - - - on chip memory - - - - - - - - - - - |
| 200 | |
| 201 | 0x00000400 ---32-----------16|15------------0- |
| 202 | | : | \ |
| 203 | | : | | |
| 204 | GERMS | : | > na_boot_monitor_rom_size |
| 205 | | : | | = 0x00000400 |
| 206 | | : | / |
| 207 | 0x00000000 |- - - - - - - - - - - - - - - -+- - nasys_reset_address |
| 208 | 0x00000000 ---32-----------16|15------------0- na_boot_monitor_rom |
| 209 | |
| 210 | |
| 211 | =============================================================================== |
| 212 | F L A S H M E M O R Y A L L O C A T I O N |
| 213 | =============================================================================== |
| 214 | |
| 215 | 0x00200000 ---15------------8|7-------------0- |
| 216 | | : | \ |
| 217 | SAFE | : | > 256 KByte |
| 218 | FPGA conf. | : | / (NOT usable by software) |
| 219 | 0x001c0000 --+- - - - - - - -:- - - - - - - -+- |
| 220 | | : | \ |
| 221 | USER | : | > 256 KByte |
| 222 | FPGA conf. | : | / (NOT usable by software) |
| 223 | 0x00180000 --+- - - - - - - -:- - - - - - - -+- |
| 224 | | : | \ |
| 225 | | : | | |
| 226 | | : | > 512 KByte free for use |
| 227 | 0x00140000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start() |
| 228 | | : | / |
| 229 | 0x00100000 ---15------------8|7-------------0- |
| 230 | |
| 231 | |
| 232 | =============================================================================== |
| 233 | R E F E R E N C E S |
| 234 | =============================================================================== |
| 235 | [1] http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf |
| 236 | [2] http://www.altera.com/literature/ds/ds_nios_uart.pdf |
| 237 | [3] http://www.altera.com/literature/ds/ds_nios_timer.pdf |
| 238 | [4] http://www.altera.com/literature/ds/ds_nios_pio.pdf |
| 239 | |
| 240 | |
| 241 | =============================================================================== |
| 242 | Stephan Linz <linz@li-pro.net> |