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Alison Wang186fc4d2012-10-18 19:25:52 +00001/*
2 * Configuation settings for the Freescale MCF54418 TWR board.
3 *
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Alison Wang186fc4d2012-10-18 19:25:52 +00008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M54418TWR_H
15#define _M54418TWR_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
Alison Wang186fc4d2012-10-18 19:25:52 +000021#define CONFIG_M54418TWR /* M54418TWR board */
22
23#define CONFIG_MCFUART
24#define CONFIG_SYS_UART_PORT (0)
Alison Wang186fc4d2012-10-18 19:25:52 +000025#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
26
27#undef CONFIG_WATCHDOG
28
29#define CONFIG_TIMESTAMP /* Print image info with timestamp */
30
31/*
32 * BOOTP options
33 */
34#define CONFIG_BOOTP_BOOTFILESIZE
35#define CONFIG_BOOTP_BOOTPATH
36#define CONFIG_BOOTP_GATEWAY
37#define CONFIG_BOOTP_HOSTNAME
38
39/* Command line configuration */
Alison Wang186fc4d2012-10-18 19:25:52 +000040#undef CONFIG_CMD_JFFS2
Alison Wang186fc4d2012-10-18 19:25:52 +000041#undef CONFIG_CMD_NAND
Alison Wang186fc4d2012-10-18 19:25:52 +000042#define CONFIG_CMD_REGINFO
Alison Wang186fc4d2012-10-18 19:25:52 +000043
44/*
45 * NAND FLASH
46 */
47#ifdef CONFIG_CMD_NAND
48#define CONFIG_JFFS2_NAND
49#define CONFIG_NAND_FSL_NFC
50#define CONFIG_SYS_NAND_BASE 0xFC0FC000
51#define CONFIG_SYS_MAX_NAND_DEVICE 1
52#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
53#define CONFIG_SYS_NAND_SELECT_DEVICE
Alison Wang186fc4d2012-10-18 19:25:52 +000054#endif
55
56/* Network configuration */
57#define CONFIG_MCFFEC
58#ifdef CONFIG_MCFFEC
Alison Wang186fc4d2012-10-18 19:25:52 +000059#define CONFIG_MII 1
60#define CONFIG_MII_INIT 1
61#define CONFIG_SYS_DISCOVER_PHY
62#define CONFIG_SYS_RX_ETH_BUFFER 2
63#define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN
64#define CONFIG_SYS_TX_ETH_BUFFER 2
65#define CONFIG_HAS_ETH1
66
67#define CONFIG_SYS_FEC0_PINMUX 0
68#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
69#define CONFIG_SYS_FEC1_PINMUX 0
70#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
71#define MCFFEC_TOUT_LOOP 50000
72#define CONFIG_SYS_FEC0_PHYADDR 0
73#define CONFIG_SYS_FEC1_PHYADDR 1
74
Alison Wang186fc4d2012-10-18 19:25:52 +000075
76#ifdef CONFIG_SYS_NAND_BOOT
77#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \
78 "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \
79 "-(jffs2) console=ttyS0,115200"
80#else
81#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \
82 __stringify(CONFIG_SERVERIP) ":/tftpboot/" \
83 __stringify(CONFIG_IPADDR) " ip=" \
84 __stringify(CONFIG_IPADDR) ":" \
85 __stringify(CONFIG_SERVERIP)":" \
86 __stringify(CONFIG_GATEWAYIP)": " \
87 __stringify(CONFIG_NETMASK) \
88 "::eth0:off:rw console=ttyS0,115200"
89#endif
90
Alison Wang186fc4d2012-10-18 19:25:52 +000091#define CONFIG_ETHPRIME "FEC0"
92#define CONFIG_IPADDR 192.168.1.2
93#define CONFIG_NETMASK 255.255.255.0
94#define CONFIG_SERVERIP 192.168.1.1
95#define CONFIG_GATEWAYIP 192.168.1.1
96
Alison Wang186fc4d2012-10-18 19:25:52 +000097#define CONFIG_SYS_FEC_BUF_USE_SRAM
98/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
99#ifndef CONFIG_SYS_DISCOVER_PHY
100#define FECDUPLEX FULL
101#define FECSPEED _100BASET
102#define LINKSTATUS 1
103#else
104#define LINKSTATUS 0
105#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
106#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
107#endif
108#endif /* CONFIG_SYS_DISCOVER_PHY */
109#endif
110
111#define CONFIG_HOSTNAME M54418TWR
112
113#if defined(CONFIG_CF_SBF)
114/* ST Micro serial flash */
115#define CONFIG_SYS_LOAD_ADDR2 0x40010007
116#define CONFIG_EXTRA_ENV_SETTINGS \
117 "netdev=eth0\0" \
118 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
119 "loadaddr=0x40010000\0" \
120 "sbfhdr=sbfhdr.bin\0" \
121 "uboot=u-boot.bin\0" \
122 "load=tftp ${loadaddr} ${sbfhdr};" \
123 "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
124 "upd=run load; run prog\0" \
125 "prog=sf probe 0:1 1000000 3;" \
126 "sf erase 0 40000;" \
127 "sf write ${loadaddr} 0 40000;" \
128 "save\0" \
129 ""
130#elif defined(CONFIG_SYS_NAND_BOOT)
131#define CONFIG_EXTRA_ENV_SETTINGS \
132 "netdev=eth0\0" \
133 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
134 "loadaddr=0x40010000\0" \
135 "u-boot=u-boot.bin\0" \
136 "load=tftp ${loadaddr} ${u-boot};\0" \
137 "upd=run load; run prog\0" \
138 "prog=nand device 0;" \
139 "nand erase 0 40000;" \
140 "nb_update ${loadaddr} ${filesize};" \
141 "save\0" \
142 ""
143#else
144#define CONFIG_SYS_UBOOT_END 0x3FFFF
145#define CONFIG_EXTRA_ENV_SETTINGS \
146 "netdev=eth0\0" \
147 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
148 "loadaddr=40010000\0" \
149 "u-boot=u-boot.bin\0" \
150 "load=tftp ${loadaddr) ${u-boot}\0" \
151 "upd=run load; run prog\0" \
152 "prog=prot off mram" " ;" \
153 "cp.b ${loadaddr} 0 ${filesize};" \
154 "save\0" \
155 ""
156#endif
157
158/* Realtime clock */
159#undef CONFIG_MCFRTC
160#define CONFIG_RTC_MCFRRTC
161#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
162
163/* Timer */
164#define CONFIG_MCFTMR
165#undef CONFIG_MCFPIT
166
167/* I2c */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200168#undef CONFIG_SYS_FSL_I2C
Alison Wang186fc4d2012-10-18 19:25:52 +0000169#undef CONFIG_HARD_I2C /* I2C with hardware support */
Heiko Schocherea818db2013-01-29 08:53:15 +0100170#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
Alison Wang186fc4d2012-10-18 19:25:52 +0000171/* I2C speed and slave address */
172#define CONFIG_SYS_I2C_SPEED 80000
173#define CONFIG_SYS_I2C_SLAVE 0x7F
174#define CONFIG_SYS_I2C_OFFSET 0x58000
175#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
176
177/* DSPI and Serial Flash */
178#define CONFIG_CF_SPI
179#define CONFIG_CF_DSPI
180#define CONFIG_SERIAL_FLASH
181#define CONFIG_HARD_SPI
182#define CONFIG_SYS_SBFHDR_SIZE 0x7
183#ifdef CONFIG_CMD_SPI
Alison Wang186fc4d2012-10-18 19:25:52 +0000184
185# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
186 DSPI_CTAR_PCSSCK_1CLK | \
187 DSPI_CTAR_PASC(0) | \
188 DSPI_CTAR_PDT(0) | \
189 DSPI_CTAR_CSSCK(0) | \
190 DSPI_CTAR_ASC(0) | \
191 DSPI_CTAR_DT(1))
192# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
193# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
194#endif
195
196/* Input, PCI, Flexbus, and VCO */
197#define CONFIG_EXTRA_CLOCK
198
199#define CONFIG_PRAM 2048 /* 2048 KB */
200
Alison Wang186fc4d2012-10-18 19:25:52 +0000201#define CONFIG_SYS_LONGHELP /* undef to save memory */
202
203#if defined(CONFIG_CMD_KGDB)
204#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
205#else
206#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
207#endif
208/* Print Buffer Size */
209#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
210 sizeof(CONFIG_SYS_PROMPT) + 16)
211#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
212/* Boot Argument Buffer Size */
213#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
214
215#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
216
Alison Wang186fc4d2012-10-18 19:25:52 +0000217#define CONFIG_SYS_MBAR 0xFC000000
218
219/*
220 * Low Level Configuration Settings
221 * (address mappings, register initial values, etc.)
222 * You should know what you are doing if you make changes here.
223 */
224
225/*-----------------------------------------------------------------------
226 * Definitions for initial stack pointer and data area (in DPRAM)
227 */
228#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
229/* End of used area in internal SRAM */
230#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
231#define CONFIG_SYS_INIT_RAM_CTRL 0x221
Alison Wang186fc4d2012-10-18 19:25:52 +0000232#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
Masahiro Yamada627b73e2014-02-07 09:23:03 +0900233 GENERATED_GBL_DATA_SIZE) - 32)
Alison Wang186fc4d2012-10-18 19:25:52 +0000234#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
235#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
236
237/*-----------------------------------------------------------------------
238 * Start addresses for the final memory configuration
239 * (Set up by the startup code)
240 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
241 */
242#define CONFIG_SYS_SDRAM_BASE 0x40000000
243#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
244
245#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
246#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
247#define CONFIG_SYS_DRAM_TEST
248
249#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
250#define CONFIG_SERIAL_BOOT
251#endif
252
253#if defined(CONFIG_SERIAL_BOOT)
Masahiro Yamada61a43922015-12-11 12:22:25 +0900254#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
Alison Wang186fc4d2012-10-18 19:25:52 +0000255#else
256#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
257#endif
258
259#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
260/* Reserve 256 kB for Monitor */
261#define CONFIG_SYS_MONITOR_LEN (256 << 10)
262/* Reserve 256 kB for malloc() */
263#define CONFIG_SYS_MALLOC_LEN (256 << 10)
264
265/*
266 * For booting Linux, the board info and command line data
267 * have to be in the first 8 MB of memory, since this is
268 * the maximum mapped by the Linux kernel during initialization ??
269 */
270/* Initial Memory map for Linux */
271#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
272 (CONFIG_SYS_SDRAM_SIZE << 20))
273
274/* Configuration for environment
275 * Environment is embedded in u-boot in the second sector of the flash
276 */
277#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
Alison Wang186fc4d2012-10-18 19:25:52 +0000278#define CONFIG_ENV_IS_IN_MRAM 1
279#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
280#define CONFIG_ENV_SIZE 0x1000
281#endif
282
283#if defined(CONFIG_CF_SBF)
Alison Wang186fc4d2012-10-18 19:25:52 +0000284#define CONFIG_ENV_IS_IN_SPI_FLASH 1
285#define CONFIG_ENV_SPI_CS 1
286#define CONFIG_ENV_OFFSET 0x40000
287#define CONFIG_ENV_SIZE 0x2000
288#define CONFIG_ENV_SECT_SIZE 0x10000
289#endif
290#if defined(CONFIG_SYS_NAND_BOOT)
Jason Jinb765fce2012-10-25 15:27:37 +0800291#define CONFIG_ENV_IS_NOWHERE
Alison Wang186fc4d2012-10-18 19:25:52 +0000292#define CONFIG_ENV_OFFSET 0x80000
293#define CONFIG_ENV_SIZE 0x20000
294#define CONFIG_ENV_SECT_SIZE 0x20000
295#endif
296#undef CONFIG_ENV_OVERWRITE
297
298/* FLASH organization */
299#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
300
301#undef CONFIG_SYS_FLASH_CFI
302#ifdef CONFIG_SYS_FLASH_CFI
303
304#define CONFIG_FLASH_CFI_DRIVER 1
305/* Max size that the board might have */
306#define CONFIG_SYS_FLASH_SIZE 0x1000000
307#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
308/* max number of memory banks */
309#define CONFIG_SYS_MAX_FLASH_BANKS 1
310/* max number of sectors on one chip */
311#define CONFIG_SYS_MAX_FLASH_SECT 270
312/* "Real" (hardware) sectors protection */
313#define CONFIG_SYS_FLASH_PROTECTION
314#define CONFIG_SYS_FLASH_CHECKSUM
315#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
316#else
317/* max number of sectors on one chip */
318#define CONFIG_SYS_MAX_FLASH_SECT 270
319/* max number of sectors on one chip */
320#define CONFIG_SYS_MAX_FLASH_BANKS 0
321#endif
322
323/*
324 * This is setting for JFFS2 support in u-boot.
325 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
326 */
327#ifdef CONFIG_CMD_JFFS2
328#define CONFIG_JFFS2_DEV "nand0"
329#define CONFIG_JFFS2_PART_OFFSET (0x800000)
330#define CONFIG_CMD_MTDPARTS
331#define CONFIG_MTD_DEVICE
332#define MTDIDS_DEFAULT "nand0=m54418twr.nand"
333
334#define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \
335 "7m(kernel)," \
336 "-(rootfs)"
337
338#endif
339
340#ifdef CONFIG_CMD_UBI
341#define CONFIG_CMD_MTDPARTS
342#define CONFIG_MTD_DEVICE /* needed for mtdparts command */
343#define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
344#define CONFIG_RBTREE
345#define MTDIDS_DEFAULT "nand0=NAND"
346#define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \
347 "-(ubi)"
348#endif
349/* Cache Configuration */
350#define CONFIG_SYS_CACHELINE_SIZE 16
351#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
352 CONFIG_SYS_INIT_RAM_SIZE - 8)
353#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
354 CONFIG_SYS_INIT_RAM_SIZE - 4)
355#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
356#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
357#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
358 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
359 CF_ACR_EN | CF_ACR_SM_ALL)
360#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
361 CF_CACR_ICINVA | CF_CACR_EUSP)
362#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
363 CF_CACR_DEC | CF_CACR_DDCM_P | \
364 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
365
366#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
367 CONFIG_SYS_INIT_RAM_SIZE - 12)
368
369/*-----------------------------------------------------------------------
370 * Memory bank definitions
371 */
372/*
373 * CS0 - NOR Flash 16MB
374 * CS1 - Available
375 * CS2 - Available
376 * CS3 - Available
377 * CS4 - Available
378 * CS5 - Available
379 */
380
381 /* Flash */
382#define CONFIG_SYS_CS0_BASE 0x00000000
383#define CONFIG_SYS_CS0_MASK 0x000F0101
384#define CONFIG_SYS_CS0_CTRL 0x00001D60
385
386#endif /* _M54418TWR_H */