Simon Glass | c3474ef | 2012-02-27 10:52:38 +0000 | [diff] [blame] | 1 | /include/ "skeleton.dtsi" |
| 2 | |
| 3 | / { |
| 4 | compatible = "nvidia,tegra20"; |
| 5 | interrupt-parent = <&intc>; |
| 6 | |
Simon Glass | eefe3e5 | 2012-10-17 13:24:48 +0000 | [diff] [blame] | 7 | host1x { |
| 8 | compatible = "nvidia,tegra20-host1x", "simple-bus"; |
| 9 | reg = <0x50000000 0x00024000>; |
| 10 | interrupts = <0 65 0x04 /* mpcore syncpt */ |
| 11 | 0 67 0x04>; /* mpcore general */ |
| 12 | status = "disabled"; |
| 13 | |
| 14 | #address-cells = <1>; |
| 15 | #size-cells = <1>; |
| 16 | |
| 17 | ranges = <0x54000000 0x54000000 0x04000000>; |
| 18 | |
| 19 | /* video-encoding/decoding */ |
| 20 | mpe { |
| 21 | reg = <0x54040000 0x00040000>; |
| 22 | interrupts = <0 68 0x04>; |
| 23 | status = "disabled"; |
| 24 | }; |
| 25 | |
| 26 | /* video input */ |
| 27 | vi { |
| 28 | reg = <0x54080000 0x00040000>; |
| 29 | interrupts = <0 69 0x04>; |
| 30 | status = "disabled"; |
| 31 | }; |
| 32 | |
| 33 | /* EPP */ |
| 34 | epp { |
| 35 | reg = <0x540c0000 0x00040000>; |
| 36 | interrupts = <0 70 0x04>; |
| 37 | status = "disabled"; |
| 38 | }; |
| 39 | |
| 40 | /* ISP */ |
| 41 | isp { |
| 42 | reg = <0x54100000 0x00040000>; |
| 43 | interrupts = <0 71 0x04>; |
| 44 | status = "disabled"; |
| 45 | }; |
| 46 | |
| 47 | /* 2D engine */ |
| 48 | gr2d { |
| 49 | reg = <0x54140000 0x00040000>; |
| 50 | interrupts = <0 72 0x04>; |
| 51 | status = "disabled"; |
| 52 | }; |
| 53 | |
| 54 | /* 3D engine */ |
| 55 | gr3d { |
| 56 | reg = <0x54180000 0x00040000>; |
| 57 | status = "disabled"; |
| 58 | }; |
| 59 | |
| 60 | /* display controllers */ |
| 61 | dc@54200000 { |
| 62 | compatible = "nvidia,tegra20-dc"; |
| 63 | reg = <0x54200000 0x00040000>; |
| 64 | interrupts = <0 73 0x04>; |
| 65 | status = "disabled"; |
| 66 | |
| 67 | rgb { |
| 68 | status = "disabled"; |
| 69 | }; |
| 70 | }; |
| 71 | |
| 72 | dc@54240000 { |
| 73 | compatible = "nvidia,tegra20-dc"; |
| 74 | reg = <0x54240000 0x00040000>; |
| 75 | interrupts = <0 74 0x04>; |
| 76 | status = "disabled"; |
| 77 | |
| 78 | rgb { |
| 79 | status = "disabled"; |
| 80 | }; |
| 81 | }; |
| 82 | |
| 83 | /* outputs */ |
| 84 | hdmi { |
| 85 | compatible = "nvidia,tegra20-hdmi"; |
| 86 | reg = <0x54280000 0x00040000>; |
| 87 | interrupts = <0 75 0x04>; |
| 88 | status = "disabled"; |
| 89 | }; |
| 90 | |
| 91 | tvo { |
| 92 | compatible = "nvidia,tegra20-tvo"; |
| 93 | reg = <0x542c0000 0x00040000>; |
| 94 | interrupts = <0 76 0x04>; |
| 95 | status = "disabled"; |
| 96 | }; |
| 97 | |
| 98 | dsi { |
| 99 | compatible = "nvidia,tegra20-dsi"; |
| 100 | reg = <0x54300000 0x00040000>; |
| 101 | status = "disabled"; |
| 102 | }; |
| 103 | }; |
| 104 | |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 105 | intc: interrupt-controller@50041000 { |
| 106 | compatible = "nvidia,tegra20-gic"; |
| 107 | interrupt-controller; |
| 108 | #interrupt-cells = <1>; |
| 109 | reg = < 0x50041000 0x1000 >, |
| 110 | < 0x50040100 0x0100 >; |
| 111 | }; |
| 112 | |
| 113 | tegra_car: clock@60006000 { |
| 114 | compatible = "nvidia,tegra20-car"; |
| 115 | reg = <0x60006000 0x1000>; |
| 116 | #clock-cells = <1>; |
| 117 | }; |
| 118 | |
Allen Martin | 64e6ec1 | 2013-01-11 23:07:04 +0000 | [diff] [blame] | 119 | apbdma: dma { |
| 120 | compatible = "nvidia,tegra20-apbdma"; |
| 121 | reg = <0x6000a000 0x1200>; |
| 122 | interrupts = <0 104 0x04 |
| 123 | 0 105 0x04 |
| 124 | 0 106 0x04 |
| 125 | 0 107 0x04 |
| 126 | 0 108 0x04 |
| 127 | 0 109 0x04 |
| 128 | 0 110 0x04 |
| 129 | 0 111 0x04 |
| 130 | 0 112 0x04 |
| 131 | 0 113 0x04 |
| 132 | 0 114 0x04 |
| 133 | 0 115 0x04 |
| 134 | 0 116 0x04 |
| 135 | 0 117 0x04 |
| 136 | 0 118 0x04 |
| 137 | 0 119 0x04>; |
| 138 | }; |
| 139 | |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 140 | gpio: gpio@6000d000 { |
| 141 | compatible = "nvidia,tegra20-gpio"; |
| 142 | reg = < 0x6000d000 0x1000 >; |
| 143 | interrupts = < 64 65 66 67 87 119 121 >; |
| 144 | #gpio-cells = <2>; |
| 145 | gpio-controller; |
| 146 | }; |
| 147 | |
| 148 | pinmux: pinmux@70000000 { |
| 149 | compatible = "nvidia,tegra20-pinmux"; |
| 150 | reg = < 0x70000014 0x10 /* Tri-state registers */ |
| 151 | 0x70000080 0x20 /* Mux registers */ |
| 152 | 0x700000a0 0x14 /* Pull-up/down registers */ |
| 153 | 0x70000868 0xa8 >; /* Pad control registers */ |
| 154 | }; |
| 155 | |
| 156 | das@70000c00 { |
| 157 | #address-cells = <1>; |
| 158 | #size-cells = <0>; |
| 159 | compatible = "nvidia,tegra20-das"; |
| 160 | reg = <0x70000c00 0x80>; |
| 161 | }; |
| 162 | |
| 163 | i2s@70002800 { |
| 164 | #address-cells = <1>; |
| 165 | #size-cells = <0>; |
| 166 | compatible = "nvidia,tegra20-i2s"; |
| 167 | reg = <0x70002800 0x200>; |
| 168 | interrupts = < 45 >; |
| 169 | dma-channel = < 2 >; |
| 170 | }; |
| 171 | |
| 172 | i2s@70002a00 { |
| 173 | #address-cells = <1>; |
| 174 | #size-cells = <0>; |
| 175 | compatible = "nvidia,tegra20-i2s"; |
| 176 | reg = <0x70002a00 0x200>; |
| 177 | interrupts = < 35 >; |
| 178 | dma-channel = < 1 >; |
| 179 | }; |
| 180 | |
| 181 | serial@70006000 { |
| 182 | compatible = "nvidia,tegra20-uart"; |
| 183 | reg = <0x70006000 0x40>; |
| 184 | reg-shift = <2>; |
| 185 | interrupts = < 68 >; |
| 186 | }; |
| 187 | |
| 188 | serial@70006040 { |
| 189 | compatible = "nvidia,tegra20-uart"; |
| 190 | reg = <0x70006040 0x40>; |
| 191 | reg-shift = <2>; |
| 192 | interrupts = < 69 >; |
| 193 | }; |
| 194 | |
| 195 | serial@70006200 { |
| 196 | compatible = "nvidia,tegra20-uart"; |
| 197 | reg = <0x70006200 0x100>; |
| 198 | reg-shift = <2>; |
| 199 | interrupts = < 78 >; |
| 200 | }; |
| 201 | |
| 202 | serial@70006300 { |
| 203 | compatible = "nvidia,tegra20-uart"; |
| 204 | reg = <0x70006300 0x100>; |
| 205 | reg-shift = <2>; |
| 206 | interrupts = < 122 >; |
| 207 | }; |
| 208 | |
| 209 | serial@70006400 { |
| 210 | compatible = "nvidia,tegra20-uart"; |
| 211 | reg = <0x70006400 0x100>; |
| 212 | reg-shift = <2>; |
| 213 | interrupts = < 123 >; |
| 214 | }; |
| 215 | |
| 216 | nand: nand-controller@70008000 { |
| 217 | #address-cells = <1>; |
| 218 | #size-cells = <0>; |
| 219 | compatible = "nvidia,tegra20-nand"; |
| 220 | reg = <0x70008000 0x100>; |
| 221 | }; |
| 222 | |
| 223 | pwm: pwm@7000a000 { |
| 224 | compatible = "nvidia,tegra20-pwm"; |
| 225 | reg = <0x7000a000 0x100>; |
| 226 | #pwm-cells = <2>; |
| 227 | }; |
| 228 | |
| 229 | i2c@7000c000 { |
| 230 | #address-cells = <1>; |
| 231 | #size-cells = <0>; |
| 232 | compatible = "nvidia,tegra20-i2c"; |
| 233 | reg = <0x7000C000 0x100>; |
| 234 | interrupts = < 70 >; |
| 235 | /* PERIPH_ID_I2C1, PLL_P_OUT3 */ |
| 236 | clocks = <&tegra_car 12>, <&tegra_car 124>; |
| 237 | }; |
| 238 | |
Allen Martin | c98f03f | 2013-01-29 13:51:23 +0000 | [diff] [blame^] | 239 | spi@7000c380 { |
| 240 | compatible = "nvidia,tegra20-sflash"; |
| 241 | reg = <0x7000c380 0x80>; |
| 242 | interrupts = <0 39 0x04>; |
| 243 | nvidia,dma-request-selector = <&apbdma 11>; |
| 244 | #address-cells = <1>; |
| 245 | #size-cells = <0>; |
| 246 | status = "disabled"; |
| 247 | /* PERIPH_ID_SPI1, PLLP_OUT0 */ |
| 248 | clocks = <&tegra_car 43>; |
| 249 | }; |
| 250 | |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 251 | i2c@7000c400 { |
| 252 | #address-cells = <1>; |
| 253 | #size-cells = <0>; |
| 254 | compatible = "nvidia,tegra20-i2c"; |
| 255 | reg = <0x7000C400 0x100>; |
| 256 | interrupts = < 116 >; |
| 257 | /* PERIPH_ID_I2C2, PLL_P_OUT3 */ |
| 258 | clocks = <&tegra_car 54>, <&tegra_car 124>; |
| 259 | }; |
| 260 | |
| 261 | i2c@7000c500 { |
| 262 | #address-cells = <1>; |
| 263 | #size-cells = <0>; |
| 264 | compatible = "nvidia,tegra20-i2c"; |
| 265 | reg = <0x7000C500 0x100>; |
| 266 | interrupts = < 124 >; |
| 267 | /* PERIPH_ID_I2C3, PLL_P_OUT3 */ |
| 268 | clocks = <&tegra_car 67>, <&tegra_car 124>; |
| 269 | }; |
| 270 | |
| 271 | i2c@7000d000 { |
| 272 | #address-cells = <1>; |
| 273 | #size-cells = <0>; |
| 274 | compatible = "nvidia,tegra20-i2c-dvc"; |
| 275 | reg = <0x7000D000 0x200>; |
| 276 | interrupts = < 85 >; |
| 277 | /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */ |
| 278 | clocks = <&tegra_car 47>, <&tegra_car 124>; |
| 279 | }; |
| 280 | |
| 281 | kbc@7000e200 { |
| 282 | compatible = "nvidia,tegra20-kbc"; |
| 283 | reg = <0x7000e200 0x0078>; |
| 284 | }; |
| 285 | |
| 286 | emc@7000f400 { |
| 287 | #address-cells = < 1 >; |
| 288 | #size-cells = < 0 >; |
| 289 | compatible = "nvidia,tegra20-emc"; |
| 290 | reg = <0x7000f400 0x200>; |
| 291 | }; |
| 292 | |
| 293 | usb@c5000000 { |
| 294 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
| 295 | reg = <0xc5000000 0x4000>; |
| 296 | interrupts = < 52 >; |
| 297 | phy_type = "utmi"; |
| 298 | clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */ |
| 299 | nvidia,has-legacy-mode; |
| 300 | }; |
| 301 | |
| 302 | usb@c5004000 { |
| 303 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
| 304 | reg = <0xc5004000 0x4000>; |
| 305 | interrupts = < 53 >; |
| 306 | phy_type = "ulpi"; |
| 307 | clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */ |
| 308 | }; |
| 309 | |
| 310 | usb@c5008000 { |
| 311 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; |
| 312 | reg = <0xc5008000 0x4000>; |
| 313 | interrupts = < 129 >; |
| 314 | phy_type = "utmi"; |
| 315 | clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */ |
| 316 | }; |
| 317 | |
| 318 | sdhci@c8000000 { |
| 319 | compatible = "nvidia,tegra20-sdhci"; |
| 320 | reg = <0xc8000000 0x200>; |
| 321 | interrupts = < 46 >; |
| 322 | }; |
| 323 | |
| 324 | sdhci@c8000200 { |
| 325 | compatible = "nvidia,tegra20-sdhci"; |
| 326 | reg = <0xc8000200 0x200>; |
| 327 | interrupts = < 47 >; |
| 328 | }; |
| 329 | |
| 330 | sdhci@c8000400 { |
| 331 | compatible = "nvidia,tegra20-sdhci"; |
| 332 | reg = <0xc8000400 0x200>; |
| 333 | interrupts = < 51 >; |
| 334 | }; |
| 335 | |
| 336 | sdhci@c8000600 { |
| 337 | compatible = "nvidia,tegra20-sdhci"; |
| 338 | reg = <0xc8000600 0x200>; |
| 339 | interrupts = < 63 >; |
| 340 | }; |
Simon Glass | c3474ef | 2012-02-27 10:52:38 +0000 | [diff] [blame] | 341 | }; |