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Stefan Roesea4c8d132006-06-02 16:18:04 +02001/*
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * pcs440ep.h - configuration for PCS440EP board
26 ***********************************************************************/
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Bartlomiej Sieka388b82f2008-03-20 23:23:13 +010030
31/* new uImage format support */
32#define CONFIG_FIT 1
33#define CONFIG_OF_LIBFDT 1
34#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
35
Stefan Roesea4c8d132006-06-02 16:18:04 +020036/*-----------------------------------------------------------------------
37 * High Level Configuration Options
38 *----------------------------------------------------------------------*/
39#define CONFIG_PCS440EP 1 /* Board is PCS440EP */
40#define CONFIG_440EP 1 /* Specific PPC440EP support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020041#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roesea4c8d132006-06-02 16:18:04 +020042#define CONFIG_4xx 1 /* ... PPC4xx family */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020043
44#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
45
Stefan Roesea4c8d132006-06-02 16:18:04 +020046#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
47
48#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
49#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
50
51/*-----------------------------------------------------------------------
52 * Base addresses -- Note these are effective addresses where the
53 * actual resources get mapped (not physical addresses)
54 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
56#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
57#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
58#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
59#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
60#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
61#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
62#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
63#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roesea4c8d132006-06-02 16:18:04 +020064
65/*Don't change either of these*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
Stefan Roesea4c8d132006-06-02 16:18:04 +020067/*Don't change either of these*/
68
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_USB_DEVICE 0x50000000
70#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
Stefan Roesea4c8d132006-06-02 16:18:04 +020071
72/*-----------------------------------------------------------------------
73 * Initial RAM & stack pointer (placed in SDRAM)
74 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
76#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
Wolfgang Denk553f0982010-10-26 13:32:32 +020077#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020078#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roesea4c8d132006-06-02 16:18:04 +020080
81/*-----------------------------------------------------------------------
82 * Serial Port
83 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020084#define CONFIG_CONS_INDEX 1 /* Use UART0 */
85#define CONFIG_SYS_NS16550
86#define CONFIG_SYS_NS16550_SERIAL
87#define CONFIG_SYS_NS16550_REG_SIZE 1
88#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */
Stefan Roesea4c8d132006-06-02 16:18:04 +020090#define CONFIG_BAUDRATE 115200
91#define CONFIG_SERIAL_MULTI 1
Stefan Roesea4c8d132006-06-02 16:18:04 +020092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roesea4c8d132006-06-02 16:18:04 +020094 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
95
96/*-----------------------------------------------------------------------
97 * Environment
98 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020099#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200100
101/*-----------------------------------------------------------------------
102 * FLASH related
103 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
105#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
108#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
111#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
112#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200115
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200116#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200117#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200119#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Heiko Schocher566a4942007-06-22 19:11:54 +0200120
121#define CONFIG_ENV_OVERWRITE 1
Stefan Roesea4c8d132006-06-02 16:18:04 +0200122
123/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200124#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
125#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200126#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200127
Heiko Schocher566a4942007-06-22 19:11:54 +0200128#define ENV_NAME_REVLEV "revision_level"
129#define ENV_NAME_SOLDER "solder_switch"
130#define ENV_NAME_DIP "dip"
131
Stefan Roesea4c8d132006-06-02 16:18:04 +0200132/*-----------------------------------------------------------------------
133 * DDR SDRAM
134 *----------------------------------------------------------------------*/
135#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
136#undef CONFIG_DDR_ECC /* don't use ECC */
Stefan Roeseed4633c2006-06-13 18:55:07 +0200137#define SPD_EEPROM_ADDRESS {0x50}
Heiko Schocher566a4942007-06-22 19:11:54 +0200138#define CONFIG_PROG_SDRAM_TLB 1
Stefan Roesea4c8d132006-06-02 16:18:04 +0200139
140/*-----------------------------------------------------------------------
141 * I2C
142 *----------------------------------------------------------------------*/
143#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
144#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200145#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
147#define CONFIG_SYS_I2C_SLAVE 0x7F
Stefan Roesea4c8d132006-06-02 16:18:04 +0200148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa4>>1)
150#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
151#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
152#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roesea4c8d132006-06-02 16:18:04 +0200153
154#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100155 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200156 "echo"
157
158#undef CONFIG_BOOTARGS
159
160#define CONFIG_EXTRA_ENV_SETTINGS \
161 "netdev=eth0\0" \
162 "hostname=pcs440ep\0" \
Heiko Schocher566a4942007-06-22 19:11:54 +0200163 "use_eeprom_ethaddr=default\0" \
164 "cs_test=off\0" \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200165 "nfsargs=setenv bootargs root=/dev/nfs rw " \
166 "nfsroot=${serverip}:${rootpath}\0" \
167 "ramargs=setenv bootargs root=/dev/ram rw\0" \
168 "addip=setenv bootargs ${bootargs} " \
169 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
170 ":${hostname}:${netdev}:off panic=1\0" \
171 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
172 "flash_nfs=run nfsargs addip addtty;" \
173 "bootm ${kernel_addr}\0" \
174 "flash_self=run ramargs addip addtty;" \
175 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
176 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
177 "bootm\0" \
178 "rootpath=/opt/eldk/ppc_4xx\0" \
179 "bootfile=/tftpboot/pcs440ep/uImage\0" \
Wolfgang Denke461a242006-06-07 11:36:02 +0200180 "kernel_addr=FFF00000\0" \
181 "ramdisk_addr=FFF00000\0" \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200182 "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \
Wolfgang Denke461a242006-06-07 11:36:02 +0200183 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
184 "cp.b 100000 FFFA0000 60000\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100185 "upd=run load update\0" \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200186 ""
187#define CONFIG_BOOTCOMMAND "run flash_self"
188
189#if 0
190#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
191#else
192#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
193#endif
194
Heiko Schocher566a4942007-06-22 19:11:54 +0200195/* check U-Boot image with SHA1 sum */
196#define CONFIG_SHA1_CHECK_UB_IMG 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SHA1_START CONFIG_SYS_MONITOR_BASE
198#define CONFIG_SHA1_LEN CONFIG_SYS_MONITOR_LEN
Heiko Schocher566a4942007-06-22 19:11:54 +0200199
200/*-----------------------------------------------------------------------
201 * Definitions for status LED
202 */
203#define CONFIG_STATUS_LED 1 /* Status LED enabled */
204#define CONFIG_BOARD_SPECIFIC_LED 1
205
Heiko Schocher96e1d752007-07-11 18:39:11 +0200206#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define STATUS_LED_PERIOD ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
Heiko Schocher566a4942007-06-22 19:11:54 +0200208#define STATUS_LED_STATE STATUS_LED_OFF
Heiko Schocher96e1d752007-07-11 18:39:11 +0200209#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define STATUS_LED_PERIOD1 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
Heiko Schocher566a4942007-06-22 19:11:54 +0200211#define STATUS_LED_STATE1 STATUS_LED_ON
Heiko Schocher96e1d752007-07-11 18:39:11 +0200212#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define STATUS_LED_PERIOD2 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
Heiko Schocher566a4942007-06-22 19:11:54 +0200214#define STATUS_LED_STATE2 STATUS_LED_OFF
Heiko Schocher96e1d752007-07-11 18:39:11 +0200215#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define STATUS_LED_PERIOD3 ((CONFIG_SYS_HZ / 2) / 5) /* blink at 5 Hz */
Heiko Schocher566a4942007-06-22 19:11:54 +0200217#define STATUS_LED_STATE3 STATUS_LED_OFF
218
219#define CONFIG_SHOW_BOOT_PROGRESS 1
220
Stefan Roesea4c8d132006-06-02 16:18:04 +0200221#define CONFIG_BAUDRATE 115200
222
223#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200225
Ben Warren96e21f82008-10-27 23:50:15 -0700226#define CONFIG_PPC4xx_EMAC
Stefan Roesea4c8d132006-06-02 16:18:04 +0200227#define CONFIG_MII 1 /* MII PHY management */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200228#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
229#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
230#define CONFIG_PHY1_ADDR 2
231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200233
234#define CONFIG_NETCONSOLE /* include NetConsole support */
235
236/* Partitions */
237#define CONFIG_MAC_PARTITION
238#define CONFIG_DOS_PARTITION
239#define CONFIG_ISO_PARTITION
240
241#ifdef CONFIG_440EP
242/* USB */
243#define CONFIG_USB_OHCI
244#define CONFIG_USB_STORAGE
245
246/*Comment this out to enable USB 1.1 device*/
247#define USB_2_0_DEVICE
248#endif /*CONFIG_440EP*/
249
250#ifdef DEBUG
251#define CONFIG_PANIC_HANG
252#else
253#define CONFIG_HW_WATCHDOG /* watchdog */
254#endif
255
Jon Loeliger26a34562007-07-04 22:33:17 -0500256
257/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500258 * BOOTP options
259 */
260#define CONFIG_BOOTP_BOOTFILESIZE
261#define CONFIG_BOOTP_BOOTPATH
262#define CONFIG_BOOTP_GATEWAY
263#define CONFIG_BOOTP_HOSTNAME
264
265
266/*
Jon Loeliger26a34562007-07-04 22:33:17 -0500267 * Command line configuration.
268 */
269#include <config_cmd_default.h>
270#define CONFIG_CMD_ASKENV
271#define CONFIG_CMD_DHCP
272#define CONFIG_CMD_DIAG
273#define CONFIG_CMD_EEPROM
274#define CONFIG_CMD_ELF
Heiko Schocherf98984c2007-08-28 17:39:14 +0200275#define CONFIG_CMD_EXT2
276#define CONFIG_CMD_FAT
Jon Loeliger26a34562007-07-04 22:33:17 -0500277#define CONFIG_CMD_I2C
Heiko Schocherf98984c2007-08-28 17:39:14 +0200278#define CONFIG_CMD_IDE
Jon Loeliger26a34562007-07-04 22:33:17 -0500279#define CONFIG_CMD_IRQ
280#define CONFIG_CMD_MII
281#define CONFIG_CMD_NET
282#define CONFIG_CMD_NFS
283#define CONFIG_CMD_PCI
284#define CONFIG_CMD_PING
285#define CONFIG_CMD_REGINFO
Heiko Schocherf98984c2007-08-28 17:39:14 +0200286#define CONFIG_CMD_REISER
Jon Loeliger26a34562007-07-04 22:33:17 -0500287#define CONFIG_CMD_SDRAM
Jon Loeliger26a34562007-07-04 22:33:17 -0500288#define CONFIG_CMD_USB
Stefan Roesea4c8d132006-06-02 16:18:04 +0200289
Stefan Roesea4c8d132006-06-02 16:18:04 +0200290#define CONFIG_SUPPORT_VFAT
291
Stefan Roesea4c8d132006-06-02 16:18:04 +0200292/*
293 * Miscellaneous configurable options
294 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_LONGHELP /* undef to save memory */
296#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger26a34562007-07-04 22:33:17 -0500297#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200299#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200301#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
303#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
304#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
307#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
310#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200311#define CONFIG_LYNXKDI 1 /* support kdi files */
312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200314
315/*-----------------------------------------------------------------------
316 * PCI stuff
317 *-----------------------------------------------------------------------
318 */
319/* General PCI */
320#define CONFIG_PCI /* include pci support */
321#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
322#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
Stefan Roesea4c8d132006-06-02 16:18:04 +0200324
325/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_PCI_TARGET_INIT
327#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roesea4c8d132006-06-02 16:18:04 +0200328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
330#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200331
332/*
333 * For booting Linux, the board info and command line data
334 * have to be in the first 8 MB of memory, since this is
335 * the maximum mapped by the Linux kernel during initialization.
336 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200338
339/*-----------------------------------------------------------------------
340 * External Bus Controller (EBC) Setup
341 *----------------------------------------------------------------------*/
342#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
343#define FLASH_BASE1_PRELIM 0xFFF80000 /* FLASH bank #1 */
344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_FLASH FLASH_BASE0_PRELIM
346#define CONFIG_SYS_SRAM 0xF1000000
347#define CONFIG_SYS_FPGA 0xF2000000
348#define CONFIG_SYS_CF1 0xF0000000
349#define CONFIG_SYS_CF2 0xF0100000
Stefan Roesea4c8d132006-06-02 16:18:04 +0200350
351/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_EBC_PB0AP 0x02010000 /* TWT=4,OEN=1 */
353#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200354
355/* Memory Bank 1 (SRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_EBC_PB1AP 0x01810040 /* TWT=3,OEN=1,BEM=1 */
357#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_SRAM | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200358
359/* Memory Bank 2 (FPGA) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_EBC_PB2AP 0x01010440 /* TWT=2,OEN=1,TH=2,BEM=1 */
361#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA | 0x5A000) /* BS=4MB,BU=R/W,BW=16bit */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200362
363/* Memory Bank 3 (CompactFlash) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_EBC_PB3AP 0x080BD400
365#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_CF1 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200366
367/* Memory Bank 4 (CompactFlash) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_EBC_PB4AP 0x080BD400
369#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CF2 | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
Stefan Roesea4c8d132006-06-02 16:18:04 +0200370
371/*-----------------------------------------------------------------------
372 * PPC440 GPIO Configuration
373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200375{ \
376/* GPIO Core 0 */ \
Stefan Roese85f73732007-06-15 07:39:43 +0200377{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
378{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
379{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
380{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
381{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
382{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
383{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \
384{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \
385{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \
386{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \
387{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \
388{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \
389{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \
390{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \
391{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \
392{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \
393{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \
394{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \
395{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \
396{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \
397{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \
398{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \
399{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \
400{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \
401{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \
402{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \
403{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \
404{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
405{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \
406{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
407{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
408{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200409}, \
410{ \
411/* GPIO Core 1 */ \
Stefan Roese85f73732007-06-15 07:39:43 +0200412{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \
413{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \
414{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
415{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
416{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \
417{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \
418{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
419{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \
420{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \
421{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \
422{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \
423{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \
424{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
425{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
426{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
427{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
428{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
429{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \
430{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \
431{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \
432{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \
433{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \
434{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \
435{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \
436{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \
437{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \
438{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \
439{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \
440{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \
441{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \
442{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \
443{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \
Stefan Roesea4c8d132006-06-02 16:18:04 +0200444} \
445}
446
Jon Loeliger26a34562007-07-04 22:33:17 -0500447#if defined(CONFIG_CMD_KGDB)
Stefan Roesea4c8d132006-06-02 16:18:04 +0200448#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
449#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
450#endif
451
Heiko Schocher566a4942007-06-22 19:11:54 +0200452/*-----------------------------------------------------------------------
453 * IDE/ATA stuff Supports IDE harddisk
454 *-----------------------------------------------------------------------
455 */
456
457#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
458
459#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
460#undef CONFIG_IDE_LED /* LED for ide not supported */
461
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
463#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
Heiko Schocher566a4942007-06-22 19:11:54 +0200464
465#define CONFIG_IDE_PREINIT 1
466#define CONFIG_IDE_RESET 1
467
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Heiko Schocher566a4942007-06-22 19:11:54 +0200469
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF1
Heiko Schocher566a4942007-06-22 19:11:54 +0200471
472/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_ATA_DATA_OFFSET 0
Heiko Schocher566a4942007-06-22 19:11:54 +0200474
475/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Heiko Schocher566a4942007-06-22 19:11:54 +0200477
478/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_ATA_ALT_OFFSET (0x0000)
Heiko Schocher566a4942007-06-22 19:11:54 +0200480
Stefan Roesea4c8d132006-06-02 16:18:04 +0200481#endif /* __CONFIG_H */