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wdenk652a10c2005-01-09 23:48:14 +00001/*
2 * (C) Copyright 2001
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * board/config.h - configuration options, board specific
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35#define CONFIG_405GP 1 /* This is a PPC405 CPU */
36#define CONFIG_4xx 1 /* ...member of PPC4xx family */
37#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
40
wdenk652a10c2005-01-09 23:48:14 +000041#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
42#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
43
44#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
45
46#define CONFIG_BAUDRATE 9600
47
48#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
49
50#define CONFIG_RAMBOOT \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010051 "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
52 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk652a10c2005-01-09 23:48:14 +000053 "bootm ffc00000 ffca0000"
54#define CONFIG_NFSBOOT \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010055 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
56 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk652a10c2005-01-09 23:48:14 +000057 "bootm ffc00000"
58
59#undef CONFIG_BOOTARGS
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */
wdenk652a10c2005-01-09 23:48:14 +000061
62
Ben Warren96e21f82008-10-27 23:50:15 -070063#define CONFIG_PPC4xx_EMAC
wdenk652a10c2005-01-09 23:48:14 +000064#define CONFIG_MII 1 /* MII PHY management */
65#define CONFIG_PHY_ADDR 0 /* PHY address */
66#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
67
68#define CONFIG_EXTRA_ENV_SETTINGS \
69 "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
70 "e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
71 "f=0x08 tn=sbc405 o=emac \0" \
72 "env_startaddr=FF000000\0" \
73 "env_endaddr=FF03FFFF\0" \
74 "loadfile=vxWorks.st\0" \
75 "loadaddr=0x01000000\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010076 "net_load=tftpboot ${loadaddr} ${loadfile}\0" \
wdenk652a10c2005-01-09 23:48:14 +000077 "uboot_startaddr=FFFC0000\0" \
78 "uboot_endaddr=FFFFFFFF\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010079 "update=tftp ${loadaddr} u-boot.bin;" \
80 "protect off ${uboot_startaddr} ${uboot_endaddr};" \
81 "era ${uboot_startaddr} ${uboot_endaddr};" \
82 "cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
83 "protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
84 "zapenv=protect off ${env_startaddr} ${env_endaddr};" \
85 "era ${env_startaddr} ${env_endaddr};" \
86 "protect on ${env_startaddr} ${env_endaddr}\0"
wdenk652a10c2005-01-09 23:48:14 +000087
88#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
89
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050090/*
91 * BOOTP options
92 */
93#define CONFIG_BOOTP_SUBNETMASK
94#define CONFIG_BOOTP_GATEWAY
95#define CONFIG_BOOTP_HOSTNAME
96#define CONFIG_BOOTP_BOOTPATH
97#define CONFIG_BOOTP_BOOTFILESIZE
98
wdenk652a10c2005-01-09 23:48:14 +000099
100#define CONFIG_ENV_OVERWRITE
101
wdenk652a10c2005-01-09 23:48:14 +0000102
Jon Loeliger866e3082007-07-04 22:30:58 -0500103/*
104 * Command line configuration.
105 */
106#include <config_cmd_default.h>
107
108#define CONFIG_CMD_BSP
109#define CONFIG_CMD_ELF
110#define CONFIG_CMD_I2C
111#define CONFIG_CMD_IRQ
112#define CONFIG_CMD_MII
113#define CONFIG_CMD_PCI
114#define CONFIG_CMD_PING
115#define CONFIG_CMD_SDRAM
116
wdenk652a10c2005-01-09 23:48:14 +0000117
118#undef CONFIG_WATCHDOG /* watchdog disabled */
119
120#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
121
122#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
123#define CONFIG_IPADDR 192.168.193.102
124#define CONFIG_NETMASK 255.255.255.224
125#define CONFIG_SERVERIP 192.168.193.119
126#define CONFIG_GATEWAYIP 192.168.193.97
127
128/*
129 * Miscellaneous configurable options
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_LONGHELP /* undef to save memory */
132#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk652a10c2005-01-09 23:48:14 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
135#ifdef CONFIG_SYS_HUSH_PARSER
136#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk652a10c2005-01-09 23:48:14 +0000137#endif
138
Jon Loeliger866e3082007-07-04 22:30:58 -0500139#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk652a10c2005-01-09 23:48:14 +0000141#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk652a10c2005-01-09 23:48:14 +0000143#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
145#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
146#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk652a10c2005-01-09 23:48:14 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
149#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk652a10c2005-01-09 23:48:14 +0000150
Stefan Roese550650d2010-09-20 16:05:31 +0200151#define CONFIG_CONS_INDEX 1 /* Use UART0 */
152#define CONFIG_SYS_NS16550
153#define CONFIG_SYS_NS16550_SERIAL
154#define CONFIG_SYS_NS16550_REG_SIZE 1
155#define CONFIG_SYS_NS16550_CLK get_serial_clock()
156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_BASE_BAUD 691200
wdenk652a10c2005-01-09 23:48:14 +0000159
160/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk652a10c2005-01-09 23:48:14 +0000162 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
163 57600, 115200, 230400, 460800, 921600 }
164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
166#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
wdenk652a10c2005-01-09 23:48:14 +0000167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk652a10c2005-01-09 23:48:14 +0000169
170#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
wdenk652a10c2005-01-09 23:48:14 +0000173
174#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
175#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200176#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
178#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk652a10c2005-01-09 23:48:14 +0000179
180/*-----------------------------------------------------------------------
181 * PCI stuff
182 *-----------------------------------------------------------------------
183 */
184#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
185#define PCI_HOST_FORCE 1 /* configure as pci host */
186#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
187
188#define CONFIG_PCI /* include pci support */
189#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
190#define CONFIG_PCI_PNP /* do pci plug-and-play */
191 /* resource configuration */
192
193#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
196#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
197#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
198#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
199#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
200#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
201#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
202#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
203#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk652a10c2005-01-09 23:48:14 +0000204
205/*-----------------------------------------------------------------------
206 * Start addresses for the final memory configuration
207 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk652a10c2005-01-09 23:48:14 +0000209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_SDRAM_BASE 0x00000000
211#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
212#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
213#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenk652a10c2005-01-09 23:48:14 +0000214
215/*
216 * For booting Linux, the board info and command line data
217 * have to be in the first 8 MB of memory, since this is
218 * the maximum mapped by the Linux kernel during initialization.
219 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk652a10c2005-01-09 23:48:14 +0000221
222/*-----------------------------------------------------------------------
223 * FLASH organization
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_FLASH_BASE 0xFF000000
226#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
227#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
228#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
229#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
230#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
231#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
232#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
233#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
234#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenk652a10c2005-01-09 23:48:14 +0000235
236/*-----------------------------------------------------------------------
237 * Environment Variable setup
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* starting right at the beginning */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200240#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200241#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
242#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
243#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
wdenk652a10c2005-01-09 23:48:14 +0000244
245/*-----------------------------------------------------------------------
wdenk652a10c2005-01-09 23:48:14 +0000246 * External Bus Controller (EBC) Setup
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define FLASH0_BA CONFIG_SYS_FLASH_BASE /* FLASH 0 Base Address */
wdenk652a10c2005-01-09 23:48:14 +0000249
250/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_EBC_PB0AP 0x92015480
252#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
wdenk652a10c2005-01-09 23:48:14 +0000253
254/*-----------------------------------------------------------------------
255 * Definitions for initial stack pointer and data area (in data cache)
256 */
257
258/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenk652a10c2005-01-09 23:48:14 +0000260
261/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
263#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenk652a10c2005-01-09 23:48:14 +0000264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200266#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200267#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk652a10c2005-01-09 23:48:14 +0000269
270/*-----------------------------------------------------------------------
271 * Definitions for Serial Presence Detect EEPROM address
272 * (to get SDRAM settings)
273 */
274#define SPD_EEPROM_ADDRESS 0x50
275#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
276
wdenk652a10c2005-01-09 23:48:14 +0000277#endif /* __CONFIG_H */