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Wolfgang Denk6cb142f2006-03-12 02:12:27 +01001/*
Aubrey.Li3f0606a2007-03-09 13:38:44 +08002 * U-boot - start.S Startup file of u-boot for BF533/BF561
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01003 *
Aubrey Li155fd762007-04-05 18:31:18 +08004 * Copyright (c) 2005-2007 Analog Devices Inc.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01005 *
6 * This file is based on head.S
7 * Copyright (c) 2003 Metrowerks/Motorola
8 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
9 * Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 * (c) 1995, Dionne & Associates
12 * (c) 1995, DKG Display Tech.
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
Aubrey Li155fd762007-04-05 18:31:18 +080029 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
30 * MA 02110-1301 USA
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010031 */
32
33/*
34 * Note: A change in this file subsequently requires a change in
Aubrey Li8db13d62007-03-10 23:49:29 +080035 * board/$(board_name)/config.mk for a valid u-boot.bin
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010036 */
37
38#define ASSEMBLY
39
40#include <linux/config.h>
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010041#include <config.h>
Aubrey.Li3f0606a2007-03-09 13:38:44 +080042#include <asm/blackfin.h>
43
44.global _stext;
45.global __bss_start;
46.global start;
47.global _start;
48.global _rambase;
49.global _ramstart;
50.global _ramend;
51.global _bf533_data_dest;
52.global _bf533_data_size;
53.global edata;
54.global _initialize;
55.global _exit;
56.global flashdataend;
57.global init_sdram;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010058
59#if (CONFIG_CCLK_DIV == 1)
60#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
61#endif
62#if (CONFIG_CCLK_DIV == 2)
63#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
64#endif
65#if (CONFIG_CCLK_DIV == 4)
66#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
67#endif
68#if (CONFIG_CCLK_DIV == 8)
69#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
70#endif
71#ifndef CONFIG_CCLK_ACT_DIV
72#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
73#endif
74
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010075.text
76_start:
77start:
78_stext:
79
Aubrey.Li3f0606a2007-03-09 13:38:44 +080080 R0 = 0x32;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010081 SYSCFG = R0;
82 SSYNC;
83
84 /* As per HW reference manual DAG registers,
Aubrey Li0d93de12007-03-12 12:11:55 +080085 * DATA and Address resgister shall be zero'd
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010086 * in initialization, after a reset state
87 */
88 r1 = 0; /* Data registers zero'd */
89 r2 = 0;
90 r3 = 0;
91 r4 = 0;
92 r5 = 0;
93 r6 = 0;
94 r7 = 0;
95
96 p0 = 0; /* Address registers zero'd */
97 p1 = 0;
98 p2 = 0;
99 p3 = 0;
100 p4 = 0;
101 p5 = 0;
Aubrey Li0d93de12007-03-12 12:11:55 +0800102
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100103 i0 = 0; /* DAG Registers zero'd */
104 i1 = 0;
105 i2 = 0;
106 i3 = 0;
107 m0 = 0;
108 m1 = 0;
109 m3 = 0;
110 m3 = 0;
111 l0 = 0;
112 l1 = 0;
113 l2 = 0;
114 l3 = 0;
115 b0 = 0;
116 b1 = 0;
117 b2 = 0;
118 b3 = 0;
119
120 /* Set loop counters to zero, to make sure that
121 * hw loops are disabled.
122 */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800123 r0 = 0;
124 lc0 = r0;
125 lc1 = r0;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100126
127 SSYNC;
128
129 /* Check soft reset status */
130 p0.h = SWRST >> 16;
131 p0.l = SWRST & 0xFFFF;
132 r0.l = w[p0];
133
134 cc = bittst(r0, 15);
135 if !cc jump no_soft_reset;
136
137 /* Clear Soft reset */
138 r0 = 0x0000;
139 w[p0] = r0;
140 ssync;
141
142no_soft_reset:
143 nop;
144
145 /* Clear EVT registers */
146 p0.h = (EVT_EMULATION_ADDR >> 16);
147 p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
148 p0 += 8;
149 p1 = 14;
150 r1 = 0;
151 LSETUP(4,4) lc0 = p1;
152 [ p0 ++ ] = r1;
Aubrey Li0d93de12007-03-12 12:11:55 +0800153
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800154 p0.h = hi(SIC_IWR);
Aubrey Li8db13d62007-03-10 23:49:29 +0800155 p0.l = lo(SIC_IWR);
156 r0.l = 0x1;
157 w[p0] = r0.l;
158 SSYNC;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100159
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800160 sp.l = (0xffb01000 & 0xFFFF);
161 sp.h = (0xffb01000 >> 16);
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100162
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800163 call init_sdram;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100164
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100165 /* relocate into to RAM */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800166 call get_pc;
167offset:
168 r2.l = offset;
169 r2.h = offset;
170 r3.l = start;
171 r3.h = start;
172 r1 = r2 - r3;
173
174 r0 = r0 - r1;
175 p1 = r0;
176
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100177 p2.l = (CFG_MONITOR_BASE & 0xffff);
178 p2.h = (CFG_MONITOR_BASE >> 16);
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800179
180 p3 = 0x04;
181 p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
182 p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100183loop1:
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800184 r1 = [p1 ++ p3];
185 [p2 ++ p3] = r1;
186 cc=p2==p4;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100187 if !cc jump loop1;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100188 /*
189 * configure STACK
190 */
191 r0.h = (CONFIG_STACKBASE >> 16);
192 r0.l = (CONFIG_STACKBASE & 0xFFFF);
193 sp = r0;
194 fp = sp;
195
196 /*
197 * This next section keeps the processor in supervisor mode
198 * during kernel boot. Switches to user mode at end of boot.
199 * See page 3-9 of Hardware Reference manual for documentation.
200 */
201
202 /* To keep ourselves in the supervisor mode */
203 p0.l = (EVT_IVG15_ADDR & 0xFFFF);
204 p0.h = (EVT_IVG15_ADDR >> 16);
205
206 p1.l = _real_start;
207 p1.h = _real_start;
208 [p0] = p1;
209
210 p0.l = (IMASK & 0xFFFF);
211 p0.h = (IMASK >> 16);
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800212 r0.l = LO(IVG15_POS);
213 r0.h = HI(IVG15_POS);
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100214 [p0] = r0;
215 raise 15;
216 p0.l = WAIT_HERE;
217 p0.h = WAIT_HERE;
218 reti = p0;
219 rti;
220
221WAIT_HERE:
222 jump WAIT_HERE;
223
224.global _real_start;
225_real_start:
226 [ -- sp ] = reti;
227
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100228 /* DMA reset code to Hi of L1 SRAM */
229copy:
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800230 /* P1 Points to the beginning of SYSTEM MMR Space */
231 P1.H = hi(SYSMMR_BASE);
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100232 P1.L = lo(SYSMMR_BASE);
233
234 R0.H = reset_start; /* Source Address (high) */
235 R0.L = reset_start; /* Source Address (low) */
236 R1.H = reset_end;
237 R1.L = reset_end;
238 R2 = R1 - R0; /* Count */
239 R1.H = hi(L1_ISRAM); /* Destination Address (high) */
240 R1.L = lo(L1_ISRAM); /* Destination Address (low) */
241 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800242 /* Destination DMAConfig Value (8-bit words) */
243 R4.L = (DI_EN | WNR | DMAEN);
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100244
245DMA:
246 R6 = 0x1 (Z);
247 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
248 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
249
250 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
251 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
252 /* Set Source DMAConfig = DMA Enable,
253 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
254 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
255
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800256 /* Set Destination Base Address */
257 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100258 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
259 /* Set Destination DMAConfig = DMA Enable,
260 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
261 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
Aubrey Li0d93de12007-03-12 12:11:55 +0800262
263WAIT_DMA_DONE:
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800264 p0.h = hi(MDMA_D0_IRQ_STATUS);
265 p0.l = lo(MDMA_D0_IRQ_STATUS);
266 R0 = W[P0](Z);
267 CC = BITTST(R0, 0);
268 if ! CC jump WAIT_DMA_DONE
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100269
270 R0 = 0x1;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100271
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800272 /* Write 1 to clear DMA interrupt */
273 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100274
275 /* Initialize BSS Section with 0 s */
276 p1.l = __bss_start;
277 p1.h = __bss_start;
278 p2.l = _end;
279 p2.h = _end;
280 r1 = p1;
281 r2 = p2;
282 r3 = r2 - r1;
283 r3 = r3 >> 2;
284 p3 = r3;
285 lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
286 CC = p2<=p1;
287 if CC jump _clear_bss_skip;
288 r0 = 0;
289_clear_bss:
290_clear_bss_end:
291 [p1++] = r0;
292_clear_bss_skip:
293
294 p0.l = _start1;
295 p0.h = _start1;
296 jump (p0);
297
298reset_start:
299 p0.h = WDOG_CNT >> 16;
300 p0.l = WDOG_CNT & 0xffff;
301 r0 = 0x0010;
302 w[p0] = r0;
303 p0.h = WDOG_CTL >> 16;
304 p0.l = WDOG_CTL & 0xffff;
305 r0 = 0x0000;
306 w[p0] = r0;
307reset_wait:
308 jump reset_wait;
309
310reset_end: nop;
311
312_exit:
313 jump.s _exit;
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800314get_pc:
315 r0 = rets;
316 rts;