| Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 1 | config RISCV_NDS |
| Bin Meng | 44fe795 | 2018-12-12 06:12:28 -0800 | [diff] [blame] | 2 | bool |
| Rick Chen | 8848474 | 2019-04-02 15:56:41 +0800 | [diff] [blame] | 3 | select ARCH_EARLY_INIT_R |
| 4 | imply CPU |
| 5 | imply CPU_RISCV |
| 6 | imply RISCV_TIMER |
| Lukas Auer | fbfd92b | 2019-08-21 21:14:43 +0200 | [diff] [blame] | 7 | imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) |
| 8 | imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) |
| Rick Chen | a8323d1 | 2019-08-29 10:30:13 +0800 | [diff] [blame] | 9 | imply V5L2_CACHE |
| Rick Chen | 52923c6 | 2018-11-07 09:34:06 +0800 | [diff] [blame] | 10 | help |
| Bin Meng | 44fe795 | 2018-12-12 06:12:28 -0800 | [diff] [blame] | 11 | Run U-Boot on AndeStar V5 platforms and use some specific features |
| 12 | which are provided by Andes Technology AndeStar V5 families. |
| 13 | |
| 14 | if RISCV_NDS |
| 15 | |
| 16 | config RISCV_NDS_CACHE |
| 17 | bool "AndeStar V5 families specific cache support" |
| Lukas Auer | fbfd92b | 2019-08-21 21:14:43 +0200 | [diff] [blame] | 18 | depends on RISCV_MMODE || SPL_RISCV_MMODE |
| Bin Meng | 44fe795 | 2018-12-12 06:12:28 -0800 | [diff] [blame] | 19 | help |
| 20 | Provide Andes Technology AndeStar V5 families specific cache support. |
| 21 | |
| 22 | endif |