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Wolfgang Denk32cb2c72006-07-21 11:31:42 +02001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2005
10 * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#include <common.h>
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070032#include <netdev.h>
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020033#include <s3c2410.h>
34
Jon Loeligerab3abcb2007-07-09 18:45:16 -050035#if defined(CONFIG_CMD_NAND)
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020036#include <linux/mtd/nand.h>
37#endif
38
Wolfgang Denk1218abf2007-09-15 20:48:41 +020039DECLARE_GLOBAL_DATA_PTR;
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020040
41#define FCLK_SPEED 1
42
43#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
44#define M_MDIV 0xC3
45#define M_PDIV 0x4
46#define M_SDIV 0x1
47#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
48#define M_MDIV 0x5c
49#define M_PDIV 0x4
50#define M_SDIV 0x0
51#endif
52
53#define USB_CLOCK 1
54
55#if USB_CLOCK==0
56#define U_M_MDIV 0xA1
57#define U_M_PDIV 0x3
58#define U_M_SDIV 0x1
59#elif USB_CLOCK==1
60#define U_M_MDIV 0x48
61#define U_M_PDIV 0x3
62#define U_M_SDIV 0x2
63#endif
64
65static inline void delay (unsigned long loops)
66{
67 __asm__ volatile ("1:\n"
68 "subs %0, %1, #1\n"
69 "bne 1b":"=r" (loops):"0" (loops));
70}
71
72/*
73 * Miscellaneous platform dependent initialisations
74 */
75
76int board_init (void)
77{
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020078 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
79 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
80
81 /* to reduce PLL lock time, adjust the LOCKTIME register */
82 clk_power->LOCKTIME = 0xFFFFFF;
83
84 /* configure MPLL */
85 clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
86
87 /* some delay between MPLL and UPLL */
88 delay (4000);
89
90 /* configure UPLL */
91 clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
92
93 /* some delay between MPLL and UPLL */
94 delay (8000);
95
96 /* set up the I/O ports */
97 gpio->GPACON = 0x007FFFFF;
98 gpio->GPBCON = 0x00044556;
99 gpio->GPBUP = 0x000007FF;
100 gpio->GPCCON = 0xAAAAAAAA;
101 gpio->GPCUP = 0x0000FFFF;
102 gpio->GPDCON = 0xAAAAAAAA;
103 gpio->GPDUP = 0x0000FFFF;
104 gpio->GPECON = 0xAAAAAAAA;
105 gpio->GPEUP = 0x0000FFFF;
106 gpio->GPFCON = 0x000055AA;
107 gpio->GPFUP = 0x000000FF;
108 gpio->GPGCON = 0xFF95FF3A;
109 gpio->GPGUP = 0x0000FFFF;
110 gpio->GPHCON = 0x0016FAAA;
111 gpio->GPHUP = 0x000007FF;
112
113 gpio->EXTINT0=0x22222222;
114 gpio->EXTINT1=0x22222222;
115 gpio->EXTINT2=0x22222222;
116
117 /* arch number of SMDK2410-Board */
118 gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
119
120 /* adress of boot parameters */
121 gd->bd->bi_boot_params = 0x30000100;
122
123 icache_enable();
124 dcache_enable();
125
126 return 0;
127}
128
129int dram_init (void)
130{
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200131 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
132 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
133
134 return 0;
135}
136
Jon Loeligerab3abcb2007-07-09 18:45:16 -0500137#if defined(CONFIG_CMD_NAND)
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200138extern ulong nand_probe(ulong physadr);
139
140static inline void NF_Reset(void)
141{
142 int i;
143
144 NF_SetCE(NFCE_LOW);
145 NF_Cmd(0xFF); /* reset command */
146 for(i = 0; i < 10; i++); /* tWB = 100ns. */
147 NF_WaitRB(); /* wait 200~500us; */
148 NF_SetCE(NFCE_HIGH);
149}
150
151static inline void NF_Init(void)
152{
153#if 1
154#define TACLS 0
155#define TWRPH0 3
156#define TWRPH1 0
157#else
158#define TACLS 0
159#define TWRPH0 4
160#define TWRPH1 2
161#endif
162
163 NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
164 /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
165 /* 1 1 1 1, 1 xxx, r xxx, r xxx */
166 /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
167
168 NF_Reset();
169}
170
171void nand_init(void)
172{
173 S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
174
175 NF_Init();
176#ifdef DEBUG
177 printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
178#endif
179 printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
180}
Jon Loeligerab3abcb2007-07-09 18:45:16 -0500181#endif
Ben Warrenb1c0eaa2009-08-25 13:09:37 -0700182
183#ifdef CONFIG_CMD_NET
184int board_eth_init(bd_t *bis)
185{
186 int rc = 0;
187#ifdef CONFIG_CS8900
188 rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
189#endif
190 return rc;
191}
192#endif