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Mike Frysinger8b219cf2008-10-12 21:54:07 -04001/*
2 * U-boot - Configuration file for cm-bf548 board
3 */
4
5#ifndef __CONFIG_CM_BF548_H__
6#define __CONFIG_CM_BF548_H__
7
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysinger8b219cf2008-10-12 21:54:07 -04009
10
11/*
12 * Processor Settings
13 */
14#define CONFIG_BFIN_CPU bf548-0.0
15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 21
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 10
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
49#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
50#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
51
52/* Default bank mapping:
53 * Async Bank 0 - 32MB Burst Flash
54 * Async Bank 1 - Ethernet
55 * Async Bank 2 - Nothing
56 * Async Bank 3 - Nothing
57 */
58#define CONFIG_EBIU_AMGCTL_VAL 0xFF
59#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
60#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
61#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
62#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
63
64#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
65#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
66
67
68/*
69 * Network Settings
70 */
71#define ADI_CMDS_NETWORK 1
Ben Warren736fead2009-07-20 22:01:11 -070072#define CONFIG_NET_MULTI
73#define CONFIG_SMC911X 1
74#define CONFIG_SMC911X_BASE 0x24000000
75#define CONFIG_SMC911X_16_BIT
Mike Frysinger8b219cf2008-10-12 21:54:07 -040076#define CONFIG_HOSTNAME cm-bf548
77/* Uncomment next line to use fixed MAC address */
78/* #define CONFIG_ETHADDR 02:80:ad:24:31:91 */
79
80
81/*
82 * Flash Settings
83 */
84#define CONFIG_FLASH_CFI_DRIVER
85#define CONFIG_SYS_FLASH_BASE 0x20000000
86#define CONFIG_SYS_FLASH_CFI
87#define CONFIG_SYS_FLASH_PROTECTION
88#define CONFIG_SYS_MAX_FLASH_BANKS 1
89#define CONFIG_SYS_MAX_FLASH_SECT 259
90
91
92/*
93 * Env Storage Settings
94 */
95#define CONFIG_ENV_IS_IN_FLASH 1
96#define CONFIG_ENV_ADDR 0x20008000
97#define CONFIG_ENV_OFFSET 0x8000
98#define CONFIG_ENV_SIZE 0x8000
99#define ENV_IS_EMBEDDED_CUSTOM
100
101
102/*
103 * I2C Settings
104 */
105#define CONFIG_BFIN_TWI_I2C 1
106#define CONFIG_HARD_I2C 1
107#define CONFIG_SYS_I2C_SPEED 50000
108#define CONFIG_SYS_I2C_SLAVE 0
109
110
111/*
112 * Misc Settings
113 */
114#define CONFIG_BAUDRATE 115200
115#define CONFIG_BOARD_EARLY_INIT_F
116#define CONFIG_RTC_BFIN
117#define CONFIG_UART_CONSOLE 1
118
119#ifndef __ADSPBF542__
120/* Don't waste time transferring a logo over the UART */
121# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
122# define CONFIG_VIDEO
123# endif
124# define CONFIG_DEB_DMA_URGENT
125#endif
126
127/* Define if want to do post memory test */
128#undef CONFIG_POST
129#ifdef CONFIG_POST
130#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
131#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
132#endif
133
134
135/*
136 * Pull in common ADI header for remaining command/environment setup
137 */
138#include <configs/bfin_adi_common.h>
139
Mike Frysinger8b219cf2008-10-12 21:54:07 -0400140#endif