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Stefano Babic28bb6d32010-04-04 23:08:03 +02001/*
2 * (C) Copyright 2010
3 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
4 *
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefano Babic28bb6d32010-04-04 23:08:03 +02008 */
9
10#ifndef __FSL_PMIC_H__
11#define __FSL_PMIC_H__
12
13/*
14 * The registers of different PMIC has the same meaning
15 * but the bit positions of the fields can differ or
16 * some fields has a meaning only on some devices.
17 * You have to check with the internal SPI bitmap
18 * (see Freescale Documentation) to set the registers
19 * for the device you are using
20 */
21enum {
22 REG_INT_STATUS0 = 0,
23 REG_INT_MASK0,
24 REG_INT_SENSE0,
25 REG_INT_STATUS1,
26 REG_INT_MASK1,
27 REG_INT_SENSE1,
28 REG_PU_MODE_S,
29 REG_IDENTIFICATION,
30 REG_UNUSED0,
31 REG_ACC0,
32 REG_ACC1, /*10 */
33 REG_UNUSED1,
34 REG_UNUSED2,
35 REG_POWER_CTL0,
36 REG_POWER_CTL1,
37 REG_POWER_CTL2,
38 REG_REGEN_ASSIGN,
39 REG_UNUSED3,
40 REG_MEM_A,
41 REG_MEM_B,
42 REG_RTC_TIME, /*20 */
43 REG_RTC_ALARM,
44 REG_RTC_DAY,
45 REG_RTC_DAY_ALARM,
46 REG_SW_0,
47 REG_SW_1,
48 REG_SW_2,
49 REG_SW_3,
50 REG_SW_4,
51 REG_SW_5,
52 REG_SETTING_0, /*30 */
53 REG_SETTING_1,
54 REG_MODE_0,
55 REG_MODE_1,
56 REG_POWER_MISC,
57 REG_UNUSED4,
58 REG_UNUSED5,
59 REG_UNUSED6,
60 REG_UNUSED7,
61 REG_UNUSED8,
62 REG_UNUSED9, /*40 */
63 REG_UNUSED10,
64 REG_UNUSED11,
65 REG_ADC0,
66 REG_ADC1,
67 REG_ADC2,
68 REG_ADC3,
69 REG_ADC4,
70 REG_CHARGE,
71 REG_USB0,
72 REG_USB1, /*50 */
73 REG_LED_CTL0,
74 REG_LED_CTL1,
75 REG_LED_CTL2,
76 REG_LED_CTL3,
77 REG_UNUSED12,
78 REG_UNUSED13,
79 REG_TRIM0,
80 REG_TRIM1,
81 REG_TEST0,
82 REG_TEST1, /*60 */
83 REG_TEST2,
84 REG_TEST3,
85 REG_TEST4,
Stefano Babicb2e5add2011-10-05 12:38:27 +020086 PMIC_NUM_OF_REGS,
Stefano Babic28bb6d32010-04-04 23:08:03 +020087};
88
89/* REG_POWER_MISC */
90#define GPO1EN (1 << 6)
91#define GPO1STBY (1 << 7)
92#define GPO2EN (1 << 8)
93#define GPO2STBY (1 << 9)
94#define GPO3EN (1 << 10)
95#define GPO3STBY (1 << 11)
96#define GPO4EN (1 << 12)
97#define GPO4STBY (1 << 13)
98#define PWGT1SPIEN (1 << 15)
99#define PWGT2SPIEN (1 << 16)
100#define PWUP (1 << 21)
101
102/* Power Control 0 */
103#define COINCHEN (1 << 23)
104#define BATTDETEN (1 << 19)
105
106/* Interrupt status 1 */
107#define RTCRSTI (1 << 7)
108
Fabio Estevam5b547f32012-05-07 10:25:59 +0000109/* MC34708 Definitions */
110#define SWx_VOLT_MASK_MC34708 0x3F
111#define SWx_1_250V_MC34708 0x30
112#define SWx_1_300V_MC34708 0x34
113#define TIMER_MASK_MC34708 0x300
114#define TIMER_4S_MC34708 0x100
115#define VUSBSEL_MC34708 (1 << 2)
116#define VUSBEN_MC34708 (1 << 3)
117#define SWBST_CTRL 31
Fabio Estevam768a0592012-05-07 10:26:00 +0000118#define SWBST_AUTO 0x8
Fabio Estevam5b547f32012-05-07 10:25:59 +0000119
Stefano Babic28bb6d32010-04-04 23:08:03 +0200120#endif