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Paul Burton25c7de22018-12-16 19:25:23 -03001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * CI20 configuration
4 *
5 * Copyright (c) 2013 Imagination Technologies
6 * Author: Paul Burton <paul.burton@imgtec.com>
7 */
8
9#ifndef __CONFIG_CI20_H__
10#define __CONFIG_CI20_H__
11
Paul Burton25c7de22018-12-16 19:25:23 -030012/* Ingenic JZ4780 clock configuration. */
Paul Burton25c7de22018-12-16 19:25:23 -030013#define CONFIG_SYS_MHZ 1200
14#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
15
16/* Memory configuration */
17#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Paul Burton25c7de22018-12-16 19:25:23 -030018
19#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
20#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
Paul Burton25c7de22018-12-16 19:25:23 -030021
Paul Burton25c7de22018-12-16 19:25:23 -030022/* NS16550-ish UARTs */
23#define CONFIG_SYS_NS16550_CLK 48000000
Paul Burton25c7de22018-12-16 19:25:23 -030024
25/* Ethernet: davicom DM9000 */
Paul Burton25c7de22018-12-16 19:25:23 -030026#define CONFIG_DM9000_BASE 0xb6000000
27#define DM9000_IO CONFIG_DM9000_BASE
28#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
29
Paul Burton25c7de22018-12-16 19:25:23 -030030/* Miscellaneous configuration options */
31#define CONFIG_SYS_BOOTM_LEN (64 << 20)
32
33/* SPL */
34#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
35
Paul Burton25c7de22018-12-16 19:25:23 -030036#define CONFIG_SPL_BSS_START_ADDR 0xf4004000
37#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */
38
39#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx"
40
Paul Burton25c7de22018-12-16 19:25:23 -030041#endif /* __CONFIG_CI20_H__ */