Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Stefan Roese <sr@denx.de> |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _CONFIG_CLEARFOG_H |
| 7 | #define _CONFIG_CLEARFOG_H |
| 8 | |
Simon Glass | 1af3c7f | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 9 | #include <linux/stringify.h> |
| 10 | |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 11 | /* |
| 12 | * High Level Configuration Options (easy to change) |
| 13 | */ |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 14 | |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 15 | /* |
| 16 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed |
| 17 | * for DDR ECC byte filling in the SPL before loading the main |
| 18 | * U-Boot into it. |
| 19 | */ |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 20 | |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 21 | #define CONFIG_ENV_MIN_ENTRIES 128 |
| 22 | |
| 23 | /* Environment in MMC */ |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 24 | /* |
| 25 | * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC |
| 26 | * boot image starts @ LBA-0. |
| 27 | * As result in MMC/eMMC case it will be a 1 sector gap between u-boot |
| 28 | * image and environment |
| 29 | */ |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 30 | |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 31 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
| 32 | |
| 33 | /* PCIe support */ |
| 34 | #ifndef CONFIG_SPL_BUILD |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 35 | #define CONFIG_PCI_SCAN_SHOW |
| 36 | #endif |
| 37 | |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 38 | /* Keep device tree and initrd in lower memory so the kernel can access them */ |
Patrick Wildt | f3d9ec2 | 2017-05-10 15:12:34 +0200 | [diff] [blame] | 39 | #define RELOCATION_LIMITS_ENV_SETTINGS \ |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 40 | "fdt_high=0x10000000\0" \ |
| 41 | "initrd_high=0x10000000\0" |
| 42 | |
| 43 | /* SPL */ |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 44 | |
| 45 | /* Defines for SPL */ |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 46 | #define CONFIG_SPL_SIZE (140 << 10) |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 47 | |
| 48 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) |
| 49 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) |
| 50 | |
| 51 | #ifdef CONFIG_SPL_BUILD |
| 52 | #define CONFIG_SYS_MALLOC_SIMPLE |
| 53 | #endif |
| 54 | |
| 55 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) |
| 56 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) |
| 57 | |
Pali Rohár | 2a85fda | 2021-07-23 11:14:32 +0200 | [diff] [blame] | 58 | #if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 59 | /* SPL related MMC defines */ |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 60 | #ifdef CONFIG_SPL_BUILD |
| 61 | #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ |
| 62 | #endif |
| 63 | #endif |
| 64 | |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 65 | /* |
| 66 | * mv-common.h should be defined after CMD configs since it used them |
| 67 | * to enable certain macros |
| 68 | */ |
| 69 | #include "mv-common.h" |
| 70 | |
Patrick Wildt | f3d9ec2 | 2017-05-10 15:12:34 +0200 | [diff] [blame] | 71 | /* Include the common distro boot environment */ |
| 72 | #ifndef CONFIG_SPL_BUILD |
Patrick Wildt | f3d9ec2 | 2017-05-10 15:12:34 +0200 | [diff] [blame] | 73 | |
| 74 | #ifdef CONFIG_MMC |
| 75 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) |
| 76 | #else |
| 77 | #define BOOT_TARGET_DEVICES_MMC(func) |
| 78 | #endif |
| 79 | |
| 80 | #ifdef CONFIG_USB_STORAGE |
| 81 | #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) |
| 82 | #else |
| 83 | #define BOOT_TARGET_DEVICES_USB(func) |
| 84 | #endif |
| 85 | |
Joel Johnson | cecf38a | 2020-03-23 11:26:32 -0600 | [diff] [blame] | 86 | #ifndef CONFIG_SCSI |
| 87 | #define BOOT_TARGET_DEVICES_SCSI_BUS0(func) |
| 88 | #define BOOT_TARGET_DEVICES_SCSI_BUS1(func) |
| 89 | #define BOOT_TARGET_DEVICES_SCSI_BUS2(func) |
Joel Johnson | bd02fd2 | 2020-03-23 11:26:31 -0600 | [diff] [blame] | 90 | #else |
Joel Johnson | cecf38a | 2020-03-23 11:26:32 -0600 | [diff] [blame] | 91 | /* |
| 92 | * With SCSI enabled, M.2 SATA is always located on bus 0 |
| 93 | */ |
| 94 | #define BOOT_TARGET_DEVICES_SCSI_BUS0(func) func(SCSI, scsi, 0) |
| 95 | |
| 96 | /* |
| 97 | * Either one or both mPCIe slots may be configured as mSATA interfaces. The |
| 98 | * SCSI bus ids are assigned based on sequence of hardware present, not always |
| 99 | * tied to hardware slot ids. As such, use second SCSI bus if either slot is |
| 100 | * set for SATA, and only use third SCSI bus if both slots are SATA enabled. |
| 101 | */ |
| 102 | #if defined (CONFIG_CLEARFOG_CON2_SATA) || defined (CONFIG_CLEARFOG_CON3_SATA) |
| 103 | #define BOOT_TARGET_DEVICES_SCSI_BUS1(func) func(SCSI, scsi, 1) |
| 104 | #else |
| 105 | #define BOOT_TARGET_DEVICES_SCSI_BUS1(func) |
Joel Johnson | bd02fd2 | 2020-03-23 11:26:31 -0600 | [diff] [blame] | 106 | #endif |
| 107 | |
Joel Johnson | cecf38a | 2020-03-23 11:26:32 -0600 | [diff] [blame] | 108 | #if defined (CONFIG_CLEARFOG_CON2_SATA) && defined (CONFIG_CLEARFOG_CON3_SATA) |
| 109 | #define BOOT_TARGET_DEVICES_SCSI_BUS2(func) func(SCSI, scsi, 2) |
| 110 | #else |
| 111 | #define BOOT_TARGET_DEVICES_SCSI_BUS2(func) |
| 112 | #endif |
| 113 | |
| 114 | #endif /* CONFIG_SCSI */ |
| 115 | |
| 116 | /* |
| 117 | * The SCSI buses are attempted in increasing bus order, there is no current |
| 118 | * mechanism to alter the default bus priority order for booting. |
| 119 | */ |
Patrick Wildt | f3d9ec2 | 2017-05-10 15:12:34 +0200 | [diff] [blame] | 120 | #define BOOT_TARGET_DEVICES(func) \ |
| 121 | BOOT_TARGET_DEVICES_MMC(func) \ |
| 122 | BOOT_TARGET_DEVICES_USB(func) \ |
Joel Johnson | cecf38a | 2020-03-23 11:26:32 -0600 | [diff] [blame] | 123 | BOOT_TARGET_DEVICES_SCSI_BUS0(func) \ |
| 124 | BOOT_TARGET_DEVICES_SCSI_BUS1(func) \ |
| 125 | BOOT_TARGET_DEVICES_SCSI_BUS2(func) \ |
Patrick Wildt | f3d9ec2 | 2017-05-10 15:12:34 +0200 | [diff] [blame] | 126 | func(PXE, pxe, na) \ |
| 127 | func(DHCP, dhcp, na) |
| 128 | |
| 129 | #define KERNEL_ADDR_R __stringify(0x800000) |
| 130 | #define FDT_ADDR_R __stringify(0x100000) |
| 131 | #define RAMDISK_ADDR_R __stringify(0x1800000) |
| 132 | #define SCRIPT_ADDR_R __stringify(0x200000) |
| 133 | #define PXEFILE_ADDR_R __stringify(0x300000) |
| 134 | |
| 135 | #define LOAD_ADDRESS_ENV_SETTINGS \ |
| 136 | "kernel_addr_r=" KERNEL_ADDR_R "\0" \ |
| 137 | "fdt_addr_r=" FDT_ADDR_R "\0" \ |
| 138 | "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ |
| 139 | "scriptaddr=" SCRIPT_ADDR_R "\0" \ |
| 140 | "pxefile_addr_r=" PXEFILE_ADDR_R "\0" |
| 141 | |
| 142 | #include <config_distro_bootcmd.h> |
| 143 | |
| 144 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 145 | RELOCATION_LIMITS_ENV_SETTINGS \ |
| 146 | LOAD_ADDRESS_ENV_SETTINGS \ |
Patrick Wildt | f3d9ec2 | 2017-05-10 15:12:34 +0200 | [diff] [blame] | 147 | "console=ttyS0,115200\0" \ |
| 148 | BOOTENV |
| 149 | |
| 150 | #endif /* CONFIG_SPL_BUILD */ |
| 151 | |
Stefan Roese | 0299c90 | 2015-10-20 15:14:47 +0200 | [diff] [blame] | 152 | #endif /* _CONFIG_CLEARFOG_H */ |