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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Albert Aribaudce9c2272010-06-17 19:38:21 +05302/*
Albert ARIBAUD57b4bce2011-04-22 19:41:02 +02003 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert Aribaudce9c2272010-06-17 19:38:21 +05304 *
5 * Based on original Kirkwood support which is
6 * (C) Copyright 2009
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Albert Aribaudce9c2272010-06-17 19:38:21 +05309 */
10
11#ifndef _CONFIG_EDMINIV2_H
12#define _CONFIG_EDMINIV2_H
13
14/*
Albert ARIBAUD9608e7d2015-01-31 22:55:38 +010015 * SPL
16 */
17
Albert ARIBAUD9608e7d2015-01-31 22:55:38 +010018#define CONFIG_SPL_STACK 0x00020000
19#define CONFIG_SPL_BSS_START_ADDR 0x00020000
20#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
21#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
22#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
Albert ARIBAUD9608e7d2015-01-31 22:55:38 +010023#define CONFIG_SYS_UBOOT_BASE 0xfff90000
24#define CONFIG_SYS_UBOOT_START 0x00800000
Albert ARIBAUD9608e7d2015-01-31 22:55:38 +010025
26/*
Albert Aribaudce9c2272010-06-17 19:38:21 +053027 * High Level Configuration Options (easy to change)
28 */
29
Lei Wen5ff8b352011-10-24 16:27:32 +000030#include <asm/arch/orion5x.h>
Albert Aribaudce9c2272010-06-17 19:38:21 +053031/*
32 * CLKs configurations
33 */
34
Albert Aribaudce9c2272010-06-17 19:38:21 +053035/*
36 * Board-specific values for Orion5x MPP low level init:
37 * - MPPs 12 to 15 are SATA LEDs (mode 5)
38 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
39 * MPP16 to MPP19, mode 0 for others
40 */
41
42#define ORION5X_MPP0_7 0x00000003
43#define ORION5X_MPP8_15 0x55550000
Albert Aribaudecaf3af2010-08-08 05:17:06 +053044#define ORION5X_MPP16_23 0x00005555
Albert Aribaudce9c2272010-06-17 19:38:21 +053045
46/*
47 * Board-specific values for Orion5x GPIO low level init:
48 * - GPIO3 is input (RTC interrupt)
49 * - GPIO16 is Power LED control (0 = on, 1 = off)
50 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
51 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
Albert ARIBAUD491f6c22012-08-16 06:35:21 +000052 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
53 * - GPIO22 is SATA disk power status ()
54 * - GPIO23 is supply status for SATA disk ()
55 * - GPIO24 is supply control for board (write 1 to power off)
56 * Last GPIO is 25, further bits are supposed to be 0.
Albert Aribaudce9c2272010-06-17 19:38:21 +053057 * Enable mask has ones for INPUT, 0 for OUTPUT.
Albert ARIBAUD491f6c22012-08-16 06:35:21 +000058 * Default is LED ON, board ON :)
Albert Aribaudce9c2272010-06-17 19:38:21 +053059 */
60
Albert ARIBAUD491f6c22012-08-16 06:35:21 +000061#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca
62#define ORION5X_GPIO_OUT_VALUE 0x00000000
63#define ORION5X_GPIO_IN_POLARITY 0x000000d0
Albert Aribaudce9c2272010-06-17 19:38:21 +053064
65/*
66 * NS16550 Configuration
67 */
68
Albert Aribaudce9c2272010-06-17 19:38:21 +053069#define CONFIG_SYS_NS16550_SERIAL
70#define CONFIG_SYS_NS16550_REG_SIZE (-4)
71#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
72#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
73
74/*
75 * Serial Port configuration
76 * The following definitions let you select what serial you want to use
77 * for your console driver.
78 */
79
Albert Aribaudce9c2272010-06-17 19:38:21 +053080#define CONFIG_SYS_BAUDRATE_TABLE \
81 { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
82
83/*
84 * FLASH configuration
85 */
86
Albert Aribaudce9c2272010-06-17 19:38:21 +053087#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
88#define CONFIG_SYS_FLASH_BASE 0xfff80000
Albert Aribaudce9c2272010-06-17 19:38:21 +053089
90/* auto boot */
Albert Aribaudce9c2272010-06-17 19:38:21 +053091
Albert Aribaudce9c2272010-06-17 19:38:21 +053092/*
Albert Aribaudab9164d2010-07-12 22:24:30 +020093 * Network
Albert Aribaudce9c2272010-06-17 19:38:21 +053094 */
Albert Aribaudab9164d2010-07-12 22:24:30 +020095
96#ifdef CONFIG_CMD_NET
Albert Aribaudab9164d2010-07-12 22:24:30 +020097#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
98#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
99#define CONFIG_PHY_BASE_ADR 0x8
Albert Aribaudab9164d2010-07-12 22:24:30 +0200100#endif
Albert Aribaudce9c2272010-06-17 19:38:21 +0530101
102/*
Albert Aribaudecaf3af2010-08-08 05:17:06 +0530103 * IDE
104 */
Simon Glassfc843a02017-05-17 03:25:30 -0600105#ifdef CONFIG_IDE
Albert Aribaudecaf3af2010-08-08 05:17:06 +0530106#define __io
Albert Aribaudecaf3af2010-08-08 05:17:06 +0530107/* Data, registers and alternate blocks are at the same offset */
Albert Aribaudecaf3af2010-08-08 05:17:06 +0530108/* Each 8-bit ATA register is aligned to a 4-bytes address */
Albert Aribaudecaf3af2010-08-08 05:17:06 +0530109/* Controller supports 48-bits LBA addressing */
110#define CONFIG_LBA48
111/* A single bus, a single device */
Albert Aribaudecaf3af2010-08-08 05:17:06 +0530112/* ATA registers base is at SATA controller base */
Albert Aribaudecaf3af2010-08-08 05:17:06 +0530113/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
Albert Aribaudecaf3af2010-08-08 05:17:06 +0530114/* end of IDE defines */
115#endif /* CMD_IDE */
116
117/*
Albert ARIBAUD81a6c002012-01-15 22:08:41 +0000118 * Common USB/EHCI configuration
119 */
120#ifdef CONFIG_CMD_USB
Albert ARIBAUD81a6c002012-01-15 22:08:41 +0000121#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
Albert ARIBAUD81a6c002012-01-15 22:08:41 +0000122#endif /* CONFIG_CMD_USB */
123
124/*
Albert Aribaudc2ca44c2010-08-27 18:26:06 +0200125 * I2C related stuff
126 */
127#ifdef CONFIG_CMD_I2C
Paul Kocialkowskidd822422015-04-10 23:09:51 +0200128#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
Albert Aribaudc2ca44c2010-08-27 18:26:06 +0200129#endif
130
131/*
Albert Aribaudce9c2272010-06-17 19:38:21 +0530132 * Environment variables configurations
133 */
Albert Aribaudce9c2272010-06-17 19:38:21 +0530134
Albert ARIBAUDa203a7c2012-02-06 20:32:19 +0530135/* Enable command line editing */
Albert ARIBAUDa203a7c2012-02-06 20:32:19 +0530136
137/* provide extensive help */
Albert ARIBAUDa203a7c2012-02-06 20:32:19 +0530138
Albert Aribaud06939232010-10-11 13:13:29 +0200139/* additions for new relocation code, must be added to all boards */
140#define CONFIG_SYS_SDRAM_BASE 0
141#define CONFIG_SYS_INIT_SP_ADDR \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200142 (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
Albert Aribaud06939232010-10-11 13:13:29 +0200143
Albert Aribaudce9c2272010-06-17 19:38:21 +0530144#endif /* _CONFIG_EDMINIV2_H */