Neil Armstrong | 485bba3 | 2018-09-05 15:56:12 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> |
| 4 | * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 9b4a205 | 2019-12-28 10:45:05 -0700 | [diff] [blame] | 8 | #include <init.h> |
Simon Glass | 90526e9 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 9 | #include <net.h> |
Neil Armstrong | d96a782 | 2018-07-27 14:10:00 +0200 | [diff] [blame] | 10 | #include <asm/arch/boot.h> |
Neil Armstrong | 485bba3 | 2018-09-05 15:56:12 +0200 | [diff] [blame] | 11 | #include <asm/arch/eth.h> |
| 12 | #include <asm/arch/axg.h> |
| 13 | #include <asm/arch/mem.h> |
| 14 | #include <asm/io.h> |
| 15 | #include <asm/armv8/mmu.h> |
| 16 | #include <linux/sizes.h> |
Neil Armstrong | e9d29b9 | 2020-09-10 10:48:17 +0200 | [diff] [blame] | 17 | #include <usb.h> |
| 18 | #include <linux/usb/otg.h> |
| 19 | #include <asm/arch/usb-gx.h> |
| 20 | #include <usb/dwc2_udc.h> |
| 21 | #include <clk.h> |
Neil Armstrong | 485bba3 | 2018-09-05 15:56:12 +0200 | [diff] [blame] | 22 | #include <phy.h> |
| 23 | |
| 24 | DECLARE_GLOBAL_DATA_PTR; |
| 25 | |
Neil Armstrong | d96a782 | 2018-07-27 14:10:00 +0200 | [diff] [blame] | 26 | int meson_get_boot_device(void) |
| 27 | { |
| 28 | return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE; |
| 29 | } |
| 30 | |
Neil Armstrong | 485bba3 | 2018-09-05 15:56:12 +0200 | [diff] [blame] | 31 | /* Configure the reserved memory zones exported by the secure registers |
| 32 | * into EFI and DTB reserved memory entries. |
| 33 | */ |
| 34 | void meson_init_reserved_memory(void *fdt) |
| 35 | { |
| 36 | u64 bl31_size, bl31_start; |
| 37 | u64 bl32_size, bl32_start; |
| 38 | u32 reg; |
| 39 | |
| 40 | /* |
| 41 | * Get ARM Trusted Firmware reserved memory zones in : |
| 42 | * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0 |
| 43 | * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL |
| 44 | * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL |
| 45 | */ |
| 46 | reg = readl(AXG_AO_SEC_GP_CFG3); |
| 47 | |
| 48 | bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK) |
| 49 | >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K; |
| 50 | bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K; |
| 51 | |
| 52 | bl31_start = readl(AXG_AO_SEC_GP_CFG5); |
| 53 | bl32_start = readl(AXG_AO_SEC_GP_CFG4); |
| 54 | |
| 55 | /* Add BL31 reserved zone */ |
| 56 | if (bl31_start && bl31_size) |
| 57 | meson_board_add_reserved_memory(fdt, bl31_start, bl31_size); |
| 58 | |
| 59 | /* Add BL32 reserved zone */ |
| 60 | if (bl32_start && bl32_size) |
| 61 | meson_board_add_reserved_memory(fdt, bl32_start, bl32_size); |
| 62 | } |
| 63 | |
| 64 | phys_size_t get_effective_memsize(void) |
| 65 | { |
| 66 | /* Size is reported in MiB, convert it in bytes */ |
| 67 | return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK) |
| 68 | >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M; |
| 69 | } |
| 70 | |
| 71 | static struct mm_region axg_mem_map[] = { |
| 72 | { |
| 73 | .virt = 0x0UL, |
| 74 | .phys = 0x0UL, |
| 75 | .size = 0x80000000UL, |
| 76 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 77 | PTE_BLOCK_INNER_SHARE |
| 78 | }, { |
| 79 | .virt = 0xf0000000UL, |
| 80 | .phys = 0xf0000000UL, |
| 81 | .size = 0x10000000UL, |
| 82 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 83 | PTE_BLOCK_NON_SHARE | |
| 84 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 85 | }, { |
| 86 | /* List terminator */ |
| 87 | 0, |
| 88 | } |
| 89 | }; |
| 90 | |
| 91 | struct mm_region *mem_map = axg_mem_map; |
| 92 | |
| 93 | /* Configure the Ethernet MAC with the requested interface mode |
| 94 | * with some optional flags. |
| 95 | */ |
| 96 | void meson_eth_init(phy_interface_t mode, unsigned int flags) |
| 97 | { |
| 98 | switch (mode) { |
| 99 | case PHY_INTERFACE_MODE_RGMII: |
| 100 | case PHY_INTERFACE_MODE_RGMII_ID: |
| 101 | case PHY_INTERFACE_MODE_RGMII_RXID: |
| 102 | case PHY_INTERFACE_MODE_RGMII_TXID: |
| 103 | /* Set RGMII mode */ |
| 104 | setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII | |
| 105 | AXG_ETH_REG_0_TX_PHASE(1) | |
| 106 | AXG_ETH_REG_0_TX_RATIO(4) | |
| 107 | AXG_ETH_REG_0_PHY_CLK_EN | |
| 108 | AXG_ETH_REG_0_CLK_EN); |
| 109 | break; |
| 110 | |
| 111 | case PHY_INTERFACE_MODE_RMII: |
| 112 | /* Set RMII mode */ |
| 113 | out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII | |
| 114 | AXG_ETH_REG_0_INVERT_RMII_CLK | |
| 115 | AXG_ETH_REG_0_CLK_EN); |
| 116 | break; |
| 117 | |
| 118 | default: |
| 119 | printf("Invalid Ethernet interface mode\n"); |
| 120 | return; |
| 121 | } |
| 122 | |
| 123 | /* Enable power gate */ |
| 124 | clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK); |
| 125 | } |
Neil Armstrong | e9d29b9 | 2020-09-10 10:48:17 +0200 | [diff] [blame] | 126 | |
| 127 | #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \ |
| 128 | CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG) |
| 129 | static struct dwc2_plat_otg_data meson_gx_dwc2_data; |
| 130 | |
| 131 | int board_usb_init(int index, enum usb_init_type init) |
| 132 | { |
| 133 | struct fdtdec_phandle_args args; |
| 134 | const void *blob = gd->fdt_blob; |
| 135 | int node, dwc2_node; |
| 136 | struct udevice *dev, *clk_dev; |
| 137 | struct clk clk; |
| 138 | int ret; |
| 139 | |
| 140 | /* find the usb glue node */ |
| 141 | node = fdt_node_offset_by_compatible(blob, -1, |
| 142 | "amlogic,meson-gxl-usb-ctrl"); |
| 143 | if (node < 0) { |
| 144 | debug("Not found usb-control node\n"); |
| 145 | return -ENODEV; |
| 146 | } |
| 147 | |
| 148 | if (!fdtdec_get_is_enabled(blob, node)) { |
| 149 | debug("usb is disabled in the device tree\n"); |
| 150 | return -ENODEV; |
| 151 | } |
| 152 | |
| 153 | ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev); |
| 154 | if (ret) { |
| 155 | debug("Not found usb-control device\n"); |
| 156 | return ret; |
| 157 | } |
| 158 | |
| 159 | /* find the dwc2 node */ |
| 160 | dwc2_node = fdt_node_offset_by_compatible(blob, node, |
| 161 | "amlogic,meson-g12a-usb"); |
| 162 | if (dwc2_node < 0) { |
| 163 | debug("Not found dwc2 node\n"); |
| 164 | return -ENODEV; |
| 165 | } |
| 166 | |
| 167 | if (!fdtdec_get_is_enabled(blob, dwc2_node)) { |
| 168 | debug("dwc2 is disabled in the device tree\n"); |
| 169 | return -ENODEV; |
| 170 | } |
| 171 | |
| 172 | meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg"); |
| 173 | if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) { |
| 174 | debug("usbotg: can't get base address\n"); |
| 175 | return -ENODATA; |
| 176 | } |
| 177 | |
| 178 | /* Enable clock */ |
| 179 | ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks", |
| 180 | "#clock-cells", 0, 0, &args); |
| 181 | if (ret) { |
| 182 | debug("usbotg has no clocks defined in the device tree\n"); |
| 183 | return ret; |
| 184 | } |
| 185 | |
| 186 | ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev); |
| 187 | if (ret) |
| 188 | return ret; |
| 189 | |
| 190 | if (args.args_count != 1) { |
| 191 | debug("Can't find clock ID in the device tree\n"); |
| 192 | return -ENODATA; |
| 193 | } |
| 194 | |
| 195 | clk.dev = clk_dev; |
| 196 | clk.id = args.args[0]; |
| 197 | |
| 198 | ret = clk_enable(&clk); |
| 199 | if (ret) { |
| 200 | debug("Failed to enable usbotg clock\n"); |
| 201 | return ret; |
| 202 | } |
| 203 | |
| 204 | meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node, |
| 205 | "g-rx-fifo-size", 0); |
| 206 | meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node, |
| 207 | "g-np-tx-fifo-size", 0); |
| 208 | meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node, |
| 209 | "g-tx-fifo-size", 0); |
| 210 | |
| 211 | /* Switch to peripheral mode */ |
| 212 | ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL); |
| 213 | if (ret) |
| 214 | return ret; |
| 215 | |
| 216 | return dwc2_udc_probe(&meson_gx_dwc2_data); |
| 217 | } |
| 218 | |
| 219 | int board_usb_cleanup(int index, enum usb_init_type init) |
| 220 | { |
| 221 | const void *blob = gd->fdt_blob; |
| 222 | struct udevice *dev; |
| 223 | int node; |
| 224 | int ret; |
| 225 | |
| 226 | /* find the usb glue node */ |
| 227 | node = fdt_node_offset_by_compatible(blob, -1, |
| 228 | "amlogic,meson-gxl-usb-ctrl"); |
| 229 | if (node < 0) { |
| 230 | debug("Not found usb-control node\n"); |
| 231 | return -ENODEV; |
| 232 | } |
| 233 | |
| 234 | if (!fdtdec_get_is_enabled(blob, node)) |
| 235 | return -ENODEV; |
| 236 | |
| 237 | ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev); |
| 238 | if (ret) |
| 239 | return ret; |
| 240 | |
| 241 | /* Switch to OTG mode */ |
| 242 | ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST); |
| 243 | if (ret) |
| 244 | return ret; |
| 245 | |
| 246 | return 0; |
| 247 | } |
| 248 | #endif |