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wdenkda27dcf2002-09-10 19:19:06 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuation settings for the LUBBOCK board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk71f95112003-06-15 22:40:42 +000021 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkda27dcf2002-09-10 19:19:06 +000022 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenkda27dcf2002-09-10 19:19:06 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010037#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */
wdenk71f95112003-06-15 22:40:42 +000038#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */
39#define CONFIG_LCD 1
wdenk63cfcbb2004-10-09 22:32:26 +000040#ifdef CONFIG_LCD
41#define CONFIG_SHARP_LM8V31
42#endif
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +010043#define CONFIG_MMC
Helmut Raiger9660e442011-10-20 04:19:47 +000044#define CONFIG_BOARD_LATE_INIT
Jean-Christophe PLAGNIOL-VILLARD10cdb8d2007-10-19 00:24:59 +020045#define CONFIG_DOS_PARTITION
Marek Vasut3c43ca22010-10-20 20:55:44 +020046#define CONFIG_SYS_TEXT_BASE 0x0
wdenkda27dcf2002-09-10 19:19:06 +000047
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020048/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000049#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020050
wdenkda27dcf2002-09-10 19:19:06 +000051/*
52 * Size of malloc() pool
53 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenkda27dcf2002-09-10 19:19:06 +000055
56/*
57 * Hardware drivers
58 */
Nishanth Menonac6b3622009-10-16 00:06:37 -050059#define CONFIG_LAN91C96
wdenk45219c42003-05-12 21:50:16 +000060#define CONFIG_LAN91C96_BASE 0x0C000000
wdenkda27dcf2002-09-10 19:19:06 +000061
62/*
63 * select serial console configuration
64 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020065#define CONFIG_PXA_SERIAL
wdenk71f95112003-06-15 22:40:42 +000066#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
Marek Vasutce6971c2012-09-12 12:36:25 +020067#define CONFIG_CONS_INDEX 3
wdenkda27dcf2002-09-10 19:19:06 +000068
69/* allow to overwrite serial and ethaddr */
70#define CONFIG_ENV_OVERWRITE
71
wdenk71f95112003-06-15 22:40:42 +000072#define CONFIG_BAUDRATE 115200
wdenkda27dcf2002-09-10 19:19:06 +000073
wdenkda27dcf2002-09-10 19:19:06 +000074
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050075/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050076 * BOOTP options
77 */
78#define CONFIG_BOOTP_BOOTFILESIZE
79#define CONFIG_BOOTP_BOOTPATH
80#define CONFIG_BOOTP_GATEWAY
81#define CONFIG_BOOTP_HOSTNAME
82
83
84/*
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050085 * Command line configuration.
86 */
87#include <config_cmd_default.h>
88
Jon Loeliger9bbb1c02007-07-04 22:32:57 -050089#define CONFIG_CMD_FAT
90
wdenkda27dcf2002-09-10 19:19:06 +000091
wdenk71f95112003-06-15 22:40:42 +000092#define CONFIG_BOOTDELAY 3
93#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
94#define CONFIG_NETMASK 255.255.0.0
95#define CONFIG_IPADDR 192.168.0.21
96#define CONFIG_SERVERIP 192.168.0.250
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +020097#define CONFIG_BOOTCOMMAND "bootm 80000"
wdenk71f95112003-06-15 22:40:42 +000098#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
99#define CONFIG_CMDLINE_TAG
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +0200100#define CONFIG_TIMESTAMP
wdenkda27dcf2002-09-10 19:19:06 +0000101
Jon Loeliger9bbb1c02007-07-04 22:32:57 -0500102#if defined(CONFIG_CMD_KGDB)
wdenk71f95112003-06-15 22:40:42 +0000103#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
104#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
wdenkda27dcf2002-09-10 19:19:06 +0000105#endif
106
107/*
108 * Miscellaneous configurable options
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_HUSH_PARSER 1
wdenk71f95112003-06-15 22:40:42 +0000111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_LONGHELP /* undef to save memory */
113#ifdef CONFIG_SYS_HUSH_PARSER
114#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
wdenk71f95112003-06-15 22:40:42 +0000115#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk71f95112003-06-15 22:40:42 +0000117#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
119#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
120#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
121#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
122#define CONFIG_SYS_DEVICE_NULLDEV 1
wdenkda27dcf2002-09-10 19:19:06 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
125#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenkda27dcf2002-09-10 19:19:06 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
wdenkda27dcf2002-09-10 19:19:06 +0000128
Micha Kalfon94a33122009-02-11 19:50:11 +0200129#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
wdenkda27dcf2002-09-10 19:19:06 +0000131
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100132#ifdef CONFIG_MMC
Marek Vasut831f8492012-09-30 10:09:49 +0000133#define CONFIG_GENERIC_MMC
134#define CONFIG_PXA_MMC_GENERIC
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100135#define CONFIG_CMD_MMC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_MMC_BASE 0xF0000000
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100137#endif
wdenkda27dcf2002-09-10 19:19:06 +0000138
139/*
wdenkda27dcf2002-09-10 19:19:06 +0000140 * Physical Memory Map
141 */
wdenk71f95112003-06-15 22:40:42 +0000142#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
143#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
144#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
145#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
146#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
147#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
148#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
149#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
150#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
wdenkda27dcf2002-09-10 19:19:06 +0000151
wdenk71f95112003-06-15 22:40:42 +0000152#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
153#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
154#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
155#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
156#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
wdenkda27dcf2002-09-10 19:19:06 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_DRAM_BASE 0xa0000000
159#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenkda27dcf2002-09-10 19:19:06 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkda27dcf2002-09-10 19:19:06 +0000162
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200163#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Marek Vasut00d5ec92011-11-26 12:04:11 +0100164#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200165
wdenkda27dcf2002-09-10 19:19:06 +0000166#define FPGA_REGS_BASE_PHYSICAL 0x08000000
167
168/*
169 * GPIO settings
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_GPSR0_VAL 0x00008000
172#define CONFIG_SYS_GPSR1_VAL 0x00FC0382
173#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF
174#define CONFIG_SYS_GPCR0_VAL 0x00000000
175#define CONFIG_SYS_GPCR1_VAL 0x00000000
176#define CONFIG_SYS_GPCR2_VAL 0x00000000
177#define CONFIG_SYS_GPDR0_VAL 0x0060A800
178#define CONFIG_SYS_GPDR1_VAL 0x00FF0382
179#define CONFIG_SYS_GPDR2_VAL 0x0001C000
180#define CONFIG_SYS_GAFR0_L_VAL 0x98400000
181#define CONFIG_SYS_GAFR0_U_VAL 0x00002950
182#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558
183#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA
184#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
185#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenkda27dcf2002-09-10 19:19:06 +0000186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_PSSR_VAL 0x20
wdenkda27dcf2002-09-10 19:19:06 +0000188
Marek Vasut3c43ca22010-10-20 20:55:44 +0200189#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
190#define CONFIG_SYS_CKEN 0x0
191
wdenkda27dcf2002-09-10 19:19:06 +0000192/*
193 * Memory settings
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_MSC0_VAL 0x23F223F2
196#define CONFIG_SYS_MSC1_VAL 0x3FF1A441
197#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1
198#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
199#define CONFIG_SYS_MDREFR_VAL 0x00018018
200#define CONFIG_SYS_MDMRS_VAL 0x00000000
wdenkda27dcf2002-09-10 19:19:06 +0000201
Marek Vasut3c43ca22010-10-20 20:55:44 +0200202#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
203#define CONFIG_SYS_SXCNFG_VAL 0x00000000
204
wdenkda27dcf2002-09-10 19:19:06 +0000205/*
206 * PCMCIA and CF Interfaces
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_MECR_VAL 0x00000000
209#define CONFIG_SYS_MCMEM0_VAL 0x00010504
210#define CONFIG_SYS_MCMEM1_VAL 0x00010504
211#define CONFIG_SYS_MCATT0_VAL 0x00010504
212#define CONFIG_SYS_MCATT1_VAL 0x00010504
213#define CONFIG_SYS_MCIO0_VAL 0x00004715
214#define CONFIG_SYS_MCIO1_VAL 0x00004715
wdenkda27dcf2002-09-10 19:19:06 +0000215
wdenk71f95112003-06-15 22:40:42 +0000216#define _LED 0x08000010
217#define LED_BLANK 0x08000040
wdenkda27dcf2002-09-10 19:19:06 +0000218
219/*
220 * FLASH and environment organization
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
223#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkda27dcf2002-09-10 19:19:06 +0000224
225/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
227#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkda27dcf2002-09-10 19:19:06 +0000228
Wolfgang Denkf2af3eb2005-09-26 00:29:53 +0200229/* NOTE: many default partitioning schemes assume the kernel starts at the
230 * second sector, not an environment. You have been warned!
231 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200233#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200234#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
235#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE
236#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16)
wdenkda27dcf2002-09-10 19:19:06 +0000237
238
239/*
240 * FPGA Offsets
241 */
wdenk71f95112003-06-15 22:40:42 +0000242#define WHOAMI_OFFSET 0x00
243#define HEXLED_OFFSET 0x10
244#define BLANKLED_OFFSET 0x40
245#define DISCRETELED_OFFSET 0x40
246#define CNFG_SWITCHES_OFFSET 0x50
247#define USER_SWITCHES_OFFSET 0x60
248#define MISC_WR_OFFSET 0x80
249#define MISC_RD_OFFSET 0x90
250#define INT_MASK_OFFSET 0xC0
251#define INT_CLEAR_OFFSET 0xD0
252#define GP_OFFSET 0x100
wdenkda27dcf2002-09-10 19:19:06 +0000253
wdenk71f95112003-06-15 22:40:42 +0000254#endif /* __CONFIG_H */