Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) Marvell International Ltd. and its affiliates |
| 3 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
| 4 | * |
Stefan Roese | 2fbc18f | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 5 | * Copyright (C) 2015 Stefan Roese <sr@denx.de> |
| 6 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
Lei Wen | a7efd71 | 2011-10-18 20:11:42 +0530 | [diff] [blame] | 11 | #include <asm/io.h> |
Stefan Roese | 3dc23f7 | 2014-10-22 12:13:06 +0200 | [diff] [blame] | 12 | #include <asm/arch/soc.h> |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 13 | |
Stefan Roese | 2fbc18f | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 14 | DECLARE_GLOBAL_DATA_PTR; |
Stefan Roese | 22700dc | 2014-10-22 12:13:08 +0200 | [diff] [blame] | 15 | |
Stefan Roese | 2fbc18f | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 16 | #define TIMER_LOAD_VAL 0xffffffff |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 17 | |
Stefan Roese | 787ddb7 | 2015-09-03 12:47:07 +0200 | [diff] [blame] | 18 | static int init_done __attribute__((section(".data"))) = 0; |
Stefan Roese | ade741b | 2015-07-15 15:36:52 +0200 | [diff] [blame] | 19 | |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 20 | /* |
Stefan Roese | 2fbc18f | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 21 | * Timer initialization |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 22 | */ |
| 23 | int timer_init(void) |
| 24 | { |
Stefan Roese | ade741b | 2015-07-15 15:36:52 +0200 | [diff] [blame] | 25 | /* Only init the timer once */ |
| 26 | if (init_done) |
| 27 | return 0; |
| 28 | init_done = 1; |
| 29 | |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 30 | /* load value into timer */ |
Stefan Roese | 2fbc18f | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 31 | writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10); |
| 32 | writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14); |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 33 | |
Stefan Roese | 81e33f4 | 2015-12-21 13:56:33 +0100 | [diff] [blame] | 34 | #if defined(CONFIG_ARCH_MVEBU) |
Stefan Roese | 2fbc18f | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 35 | /* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */ |
| 36 | setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11)); |
| 37 | #endif |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 38 | /* enable timer in auto reload mode */ |
Stefan Roese | 2fbc18f | 2015-10-22 12:36:31 +0200 | [diff] [blame] | 39 | setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3); |
Prafulla Wadaskar | 4efb77d | 2009-06-20 11:01:53 +0200 | [diff] [blame] | 40 | |
| 41 | return 0; |
| 42 | } |