Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Heiko Schocher | c0dcece | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 2 | /* |
Enrico Leto | d89a97e | 2024-01-24 15:43:53 +0100 | [diff] [blame] | 3 | * Board definitions for draco products |
Heiko Schocher | c0dcece | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 4 | * |
| 5 | * (C) Copyright 2013 Siemens Schweiz AG |
| 6 | * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. |
| 7 | * |
Enrico Leto | d89a97e | 2024-01-24 15:43:53 +0100 | [diff] [blame] | 8 | * TI am335x specifics moved to ../common/board_am335x.h |
Heiko Schocher | c0dcece | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 9 | */ |
| 10 | |
Enrico Leto | d89a97e | 2024-01-24 15:43:53 +0100 | [diff] [blame] | 11 | #ifndef _BOARD_DRACO_H_ |
| 12 | #define _BOARD_DRACO_H_ |
Heiko Schocher | c0dcece | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 13 | |
Heiko Schocher | 61159b7 | 2015-06-16 14:59:34 +0200 | [diff] [blame] | 14 | #define PARGS(x) #x , /* Parameter Name */ \ |
| 15 | settings.ddr3.x, /* EEPROM Value */ \ |
| 16 | ddr3_default.x, /* Default Value */ \ |
| 17 | settings.ddr3.x-ddr3_default.x /* Difference */ |
| 18 | |
| 19 | #define PRINTARGS(y) printf("%-20s, %8x, %8x, %4d\n", PARGS(y)) |
| 20 | |
Heiko Schocher | c0dcece | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 21 | #define MAGIC_CHIP 0x50494843 |
| 22 | |
| 23 | /* Automatic generated definition */ |
Egli, Samuel | 823b2c4 | 2014-04-24 17:57:53 +0200 | [diff] [blame] | 24 | /* Wed, 16 Apr 2014 16:50:41 +0200 */ |
| 25 | /* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */ |
Heiko Schocher | c0dcece | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 26 | struct ddr3_data { |
| 27 | unsigned int magic; /* 0x33524444 */ |
Egli, Samuel | 823b2c4 | 2014-04-24 17:57:53 +0200 | [diff] [blame] | 28 | unsigned int version; /* 0x56312e35 */ |
| 29 | unsigned short int ddr3_sratio; /* 0x0080 */ |
| 30 | unsigned short int iclkout; /* 0x0000 */ |
Heiko Schocher | c0dcece | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 31 | unsigned short int dt0rdsratio0; /* 0x003A */ |
Egli, Samuel | 823b2c4 | 2014-04-24 17:57:53 +0200 | [diff] [blame] | 32 | unsigned short int dt0wdsratio0; /* 0x003F */ |
| 33 | unsigned short int dt0fwsratio0; /* 0x009F */ |
| 34 | unsigned short int dt0wrsratio0; /* 0x0079 */ |
Heiko Schocher | c0dcece | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 35 | unsigned int sdram_tim1; /* 0x0888A39B */ |
| 36 | unsigned int sdram_tim2; /* 0x26247FDA */ |
| 37 | unsigned int sdram_tim3; /* 0x501F821F */ |
Samuel Egli | 56eb3da | 2013-11-04 14:05:03 +0100 | [diff] [blame] | 38 | unsigned int emif_ddr_phy_ctlr_1; /* 0x00100206 */ |
Egli, Samuel | 823b2c4 | 2014-04-24 17:57:53 +0200 | [diff] [blame] | 39 | unsigned int sdram_config; /* 0x61A44A32 */ |
| 40 | unsigned int ref_ctrl; /* 0x0000093B */ |
| 41 | unsigned int ioctr_val; /* 0x0000014A */ |
| 42 | char manu_name[32]; /* "default@303MHz \0" */ |
| 43 | char manu_marking[32]; /* "default \0" */ |
Heiko Schocher | c0dcece | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 44 | }; |
| 45 | |
| 46 | struct chip_data { |
| 47 | unsigned int magic; |
| 48 | char sdevname[16]; |
| 49 | char shwver[7]; |
| 50 | }; |
| 51 | |
Egli, Samuel | 820969f | 2014-05-05 16:50:43 +0200 | [diff] [blame] | 52 | struct draco_baseboard_id { |
Heiko Schocher | c0dcece | 2013-08-19 16:39:01 +0200 | [diff] [blame] | 53 | struct ddr3_data ddr3; |
| 54 | struct chip_data chip; |
| 55 | }; |
| 56 | |
Enrico Leto | d89a97e | 2024-01-24 15:43:53 +0100 | [diff] [blame] | 57 | #endif /* _BOARD_DRACO_H_ */ |