blob: aa5cfc6e41d55ee5da142a8228576f37d949706e [file] [log] [blame]
Patrick Delaunay44abcf62022-05-20 18:24:52 +02001// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
2/*
3 * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
4 */
5
6/ {
7 aliases {
8 gpio0 = &gpioa;
9 gpio1 = &gpiob;
10 gpio2 = &gpioc;
11 gpio3 = &gpiod;
12 gpio4 = &gpioe;
13 gpio5 = &gpiof;
14 gpio6 = &gpiog;
15 gpio7 = &gpioh;
16 gpio8 = &gpioi;
17 pinctrl0 = &pinctrl;
18 };
19
Patrick Delaunay152498d2022-09-07 13:42:23 +020020 firmware {
21 optee {
Simon Glass8c103c32023-02-13 08:56:33 -070022 bootph-all;
Patrick Delaunay152498d2022-09-07 13:42:23 +020023 };
24 };
25
Patrick Delaunay44abcf62022-05-20 18:24:52 +020026 /* need PSCI for sysreset during board_f */
27 psci {
Simon Glass8c103c32023-02-13 08:56:33 -070028 bootph-some-ram;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020029 };
30
31 soc {
Simon Glass8c103c32023-02-13 08:56:33 -070032 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020033
34 ddr: ddr@5a003000 {
Simon Glass8c103c32023-02-13 08:56:33 -070035 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020036
37 compatible = "st,stm32mp13-ddr";
38
39 reg = <0x5A003000 0x550
40 0x5A004000 0x234>;
41
42 status = "okay";
43 };
44 };
45};
46
47&bsec {
Simon Glass8c103c32023-02-13 08:56:33 -070048 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020049};
50
51&gpioa {
Simon Glass8c103c32023-02-13 08:56:33 -070052 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020053};
54
55&gpiob {
Simon Glass8c103c32023-02-13 08:56:33 -070056 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020057};
58
59&gpioc {
Simon Glass8c103c32023-02-13 08:56:33 -070060 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020061};
62
63&gpiod {
Simon Glass8c103c32023-02-13 08:56:33 -070064 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020065};
66
67&gpioe {
Simon Glass8c103c32023-02-13 08:56:33 -070068 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020069};
70
71&gpiof {
Simon Glass8c103c32023-02-13 08:56:33 -070072 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020073};
74
75&gpiog {
Simon Glass8c103c32023-02-13 08:56:33 -070076 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020077};
78
79&gpioh {
Simon Glass8c103c32023-02-13 08:56:33 -070080 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020081};
82
83&gpioi {
Simon Glass8c103c32023-02-13 08:56:33 -070084 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020085};
86
87&iwdg2 {
Simon Glass8c103c32023-02-13 08:56:33 -070088 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020089};
90
Patrick Delaunay44abcf62022-05-20 18:24:52 +020091&pinctrl {
Simon Glass8c103c32023-02-13 08:56:33 -070092 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +020093};
94
Gabriel Fernandez2c8d5482022-11-24 11:36:05 +010095&rcc {
Simon Glass8c103c32023-02-13 08:56:33 -070096 bootph-all;
Gabriel Fernandez2c8d5482022-11-24 11:36:05 +010097};
98
Patrick Delaunay44db0982022-07-06 18:20:25 +020099&scmi {
Simon Glass8c103c32023-02-13 08:56:33 -0700100 bootph-all;
Patrick Delaunay44db0982022-07-06 18:20:25 +0200101};
102
103&scmi_clk {
Simon Glass8c103c32023-02-13 08:56:33 -0700104 bootph-all;
Patrick Delaunay44db0982022-07-06 18:20:25 +0200105};
106
107&scmi_reset {
Simon Glass8c103c32023-02-13 08:56:33 -0700108 bootph-all;
Patrick Delaunay44db0982022-07-06 18:20:25 +0200109};
110
Patrick Delaunay44abcf62022-05-20 18:24:52 +0200111&syscfg {
Simon Glass8c103c32023-02-13 08:56:33 -0700112 bootph-all;
Patrick Delaunay44abcf62022-05-20 18:24:52 +0200113};