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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkbf9e3b32004-02-12 00:47:09 +00002/*
3 * Configuation settings for the Motorola MC5282EVB board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
wdenkbf9e3b32004-02-12 00:47:09 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
wdenk4e5ca3e2003-12-08 01:34:36 +000012#ifndef _CONFIG_M5282EVB_H
13#define _CONFIG_M5282EVB_H
14
wdenkbf9e3b32004-02-12 00:47:09 +000015/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050019#define CONFIG_MCFTMR
wdenk4e5ca3e2003-12-08 01:34:36 +000020
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050021#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#define CONFIG_SYS_UART_PORT (0)
wdenkbf9e3b32004-02-12 00:47:09 +000023
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050024#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
wdenkbf9e3b32004-02-12 00:47:09 +000025
26/* Configuration for environment
27 * Environment is embedded in u-boot in the second sector of the flash
28 */
wdenkbf9e3b32004-02-12 00:47:09 +000029
angelo@sysam.it5296cb12015-03-29 22:54:16 +020030#define LDS_BOARD_TEXT \
31 . = DEFINED(env_offset) ? env_offset : .; \
Simon Glass0649cd02017-08-03 12:21:49 -060032 env/embedded.o(.text*);
angelo@sysam.it5296cb12015-03-29 22:54:16 +020033
Jon Loeliger8353e132007-07-08 14:14:17 -050034/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050035 * BOOTP options
36 */
37#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeliger659e2f62007-07-10 09:10:49 -050038
Jon Loeliger659e2f62007-07-10 09:10:49 -050039/*
Jon Loeliger8353e132007-07-08 14:14:17 -050040 * Command line configuration.
41 */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050042#ifdef CONFIG_MCFFEC
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050043# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044# define CONFIG_SYS_DISCOVER_PHY
45# define CONFIG_SYS_RX_ETH_BUFFER 8
46# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
48# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050049# define FECDUPLEX FULL
50# define FECSPEED _100BASET
51# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
53# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050054# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050056#endif
Jon Loeliger8353e132007-07-08 14:14:17 -050057
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050058#ifdef CONFIG_MCFFEC
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050059# define CONFIG_IPADDR 192.162.1.2
60# define CONFIG_NETMASK 255.255.255.0
61# define CONFIG_SERVERIP 192.162.1.1
62# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050063#endif /* CONFIG_MCFFEC */
64
Mario Six5bc05432018-03-28 14:38:20 +020065#define CONFIG_HOSTNAME "M5282EVB"
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050066#define CONFIG_EXTRA_ENV_SETTINGS \
67 "netdev=eth0\0" \
68 "loadaddr=10000\0" \
69 "u-boot=u-boot.bin\0" \
70 "load=tftp ${loadaddr) ${u-boot}\0" \
71 "upd=run load; run prog\0" \
72 "prog=prot off ffe00000 ffe3ffff;" \
73 "era ffe00000 ffe3ffff;" \
74 "cp.b ${loadaddr} ffe00000 ${filesize};"\
75 "save\0" \
76 ""
wdenkbf9e3b32004-02-12 00:47:09 +000077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_LOAD_ADDR 0x20000
wdenkbf9e3b32004-02-12 00:47:09 +000079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_CLK 64000000
wdenkbf9e3b32004-02-12 00:47:09 +000081
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050082/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
85#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
wdenkbf9e3b32004-02-12 00:47:09 +000086
87/*
88 * Low Level Configuration Settings
89 * (address mappings, register initial values, etc.)
90 * You should know what you are doing if you make changes here.
91 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_MBAR 0x40000000
wdenkbf9e3b32004-02-12 00:47:09 +000093
wdenkbf9e3b32004-02-12 00:47:09 +000094/*-----------------------------------------------------------------------
95 * Definitions for initial stack pointer and data area (in DPRAM)
96 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +020098#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020099#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkbf9e3b32004-02-12 00:47:09 +0000101
102/*-----------------------------------------------------------------------
103 * Start addresses for the final memory configuration
104 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkbf9e3b32004-02-12 00:47:09 +0000106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_SDRAM_BASE 0x00000000
108#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liew012522f2008-10-21 10:03:07 +0000109#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
111#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
wdenkbf9e3b32004-02-12 00:47:09 +0000112
113/* If M5282 port is fully implemented the monitor base will be behind
114 * the vector table. */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200115#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500117#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200118#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500119#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_MONITOR_LEN 0x20000
122#define CONFIG_SYS_MALLOC_LEN (256 << 10)
123#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkbf9e3b32004-02-12 00:47:09 +0000124
wdenkbf9e3b32004-02-12 00:47:09 +0000125/*
126 * For booting Linux, the board info and command line data
127 * have to be in the first 8 MB of memory, since this is
128 * the maximum mapped by the Linux kernel during initialization ??
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
wdenkbf9e3b32004-02-12 00:47:09 +0000131
132/*-----------------------------------------------------------------------
133 * FLASH organization
134 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#ifdef CONFIG_SYS_FLASH_CFI
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
138# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
139# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
140# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141# define CONFIG_SYS_FLASH_CHECKSUM
142# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500143#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000144
145/*-----------------------------------------------------------------------
146 * Cache Configuration
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkbf9e3b32004-02-12 00:47:09 +0000149
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600150#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200151 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600152#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200153 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600154#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
155#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
156 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
157 CF_ACR_EN | CF_ACR_SM_ALL)
158#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
159 CF_CACR_CEIB | CF_CACR_DBWE | \
160 CF_CACR_EUSP)
161
wdenkbf9e3b32004-02-12 00:47:09 +0000162/*-----------------------------------------------------------------------
163 * Memory bank definitions
164 */
TsiChung Liew012522f2008-10-21 10:03:07 +0000165#define CONFIG_SYS_CS0_BASE 0xFFE00000
166#define CONFIG_SYS_CS0_CTRL 0x00001980
167#define CONFIG_SYS_CS0_MASK 0x001F0001
168
wdenkbf9e3b32004-02-12 00:47:09 +0000169/*-----------------------------------------------------------------------
170 * Port configuration
171 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
173#define CONFIG_SYS_PADDR 0x0000000
174#define CONFIG_SYS_PADAT 0x0000000
wdenkbf9e3b32004-02-12 00:47:09 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
177#define CONFIG_SYS_PBDDR 0x0000000
178#define CONFIG_SYS_PBDAT 0x0000000
wdenk4e5ca3e2003-12-08 01:34:36 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
181#define CONFIG_SYS_PCDDR 0x0000000
182#define CONFIG_SYS_PCDAT 0x0000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
185#define CONFIG_SYS_PCDDR 0x0000000
186#define CONFIG_SYS_PCDAT 0x0000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_PEHLPAR 0xC0
189#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
190#define CONFIG_SYS_DDRUA 0x05
191#define CONFIG_SYS_PJPAR 0xFF
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500192
193#endif /* _CONFIG_M5282EVB_H */