Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the Motorola MC5282EVB board. |
| 4 | * |
| 5 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * board/config.h - configuration options, board specific |
| 10 | */ |
| 11 | |
wdenk | 4e5ca3e | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 12 | #ifndef _CONFIG_M5282EVB_H |
| 13 | #define _CONFIG_M5282EVB_H |
| 14 | |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 15 | /* |
| 16 | * High Level Configuration Options |
| 17 | * (easy to change) |
| 18 | */ |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 19 | #define CONFIG_MCFTMR |
wdenk | 4e5ca3e | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 20 | |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 21 | #define CONFIG_MCFUART |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 22 | #define CONFIG_SYS_UART_PORT (0) |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 23 | |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 24 | #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 25 | |
| 26 | /* Configuration for environment |
| 27 | * Environment is embedded in u-boot in the second sector of the flash |
| 28 | */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 29 | |
angelo@sysam.it | 5296cb1 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 30 | #define LDS_BOARD_TEXT \ |
| 31 | . = DEFINED(env_offset) ? env_offset : .; \ |
Simon Glass | 0649cd0 | 2017-08-03 12:21:49 -0600 | [diff] [blame] | 32 | env/embedded.o(.text*); |
angelo@sysam.it | 5296cb1 | 2015-03-29 22:54:16 +0200 | [diff] [blame] | 33 | |
Jon Loeliger | 8353e13 | 2007-07-08 14:14:17 -0500 | [diff] [blame] | 34 | /* |
Jon Loeliger | 659e2f6 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 35 | * BOOTP options |
| 36 | */ |
| 37 | #define CONFIG_BOOTP_BOOTFILESIZE |
Jon Loeliger | 659e2f6 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 38 | |
Jon Loeliger | 659e2f6 | 2007-07-10 09:10:49 -0500 | [diff] [blame] | 39 | /* |
Jon Loeliger | 8353e13 | 2007-07-08 14:14:17 -0500 | [diff] [blame] | 40 | * Command line configuration. |
| 41 | */ |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 42 | #ifdef CONFIG_MCFFEC |
TsiChung Liew | 0f3ba7e | 2008-03-30 01:22:13 -0500 | [diff] [blame] | 43 | # define CONFIG_MII_INIT 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 44 | # define CONFIG_SYS_DISCOVER_PHY |
| 45 | # define CONFIG_SYS_RX_ETH_BUFFER 8 |
| 46 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
| 48 | # ifndef CONFIG_SYS_DISCOVER_PHY |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 49 | # define FECDUPLEX FULL |
| 50 | # define FECSPEED _100BASET |
| 51 | # else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 53 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 54 | # endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 55 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 56 | #endif |
Jon Loeliger | 8353e13 | 2007-07-08 14:14:17 -0500 | [diff] [blame] | 57 | |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 58 | #ifdef CONFIG_MCFFEC |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 59 | # define CONFIG_IPADDR 192.162.1.2 |
| 60 | # define CONFIG_NETMASK 255.255.255.0 |
| 61 | # define CONFIG_SERVERIP 192.162.1.1 |
| 62 | # define CONFIG_GATEWAYIP 192.162.1.1 |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 63 | #endif /* CONFIG_MCFFEC */ |
| 64 | |
Mario Six | 5bc0543 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 65 | #define CONFIG_HOSTNAME "M5282EVB" |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 66 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 67 | "netdev=eth0\0" \ |
| 68 | "loadaddr=10000\0" \ |
| 69 | "u-boot=u-boot.bin\0" \ |
| 70 | "load=tftp ${loadaddr) ${u-boot}\0" \ |
| 71 | "upd=run load; run prog\0" \ |
| 72 | "prog=prot off ffe00000 ffe3ffff;" \ |
| 73 | "era ffe00000 ffe3ffff;" \ |
| 74 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ |
| 75 | "save\0" \ |
| 76 | "" |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 77 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 78 | #define CONFIG_SYS_LOAD_ADDR 0x20000 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 79 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 80 | #define CONFIG_SYS_CLK 64000000 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 81 | |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 82 | /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ |
| 83 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 84 | #define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ |
| 85 | #define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 86 | |
| 87 | /* |
| 88 | * Low Level Configuration Settings |
| 89 | * (address mappings, register initial values, etc.) |
| 90 | * You should know what you are doing if you make changes here. |
| 91 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_MBAR 0x40000000 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 93 | |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 94 | /*----------------------------------------------------------------------- |
| 95 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 96 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 97 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 98 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 99 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 100 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 101 | |
| 102 | /*----------------------------------------------------------------------- |
| 103 | * Start addresses for the final memory configuration |
| 104 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 105 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 106 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 107 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 108 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 109 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 |
| 111 | #define CONFIG_SYS_INT_FLASH_ENABLE 0x21 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 112 | |
| 113 | /* If M5282 port is fully implemented the monitor base will be behind |
| 114 | * the vector table. */ |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 115 | #if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 116 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 117 | #else |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 118 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 119 | #endif |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 120 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 121 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
| 122 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) |
| 123 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 124 | |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 125 | /* |
| 126 | * For booting Linux, the board info and command line data |
| 127 | * have to be in the first 8 MB of memory, since this is |
| 128 | * the maximum mapped by the Linux kernel during initialization ?? |
| 129 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 130 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 131 | |
| 132 | /*----------------------------------------------------------------------- |
| 133 | * FLASH organization |
| 134 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 135 | #ifdef CONFIG_SYS_FLASH_CFI |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 136 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 137 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
| 138 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| 139 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 140 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 141 | # define CONFIG_SYS_FLASH_CHECKSUM |
| 142 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 143 | #endif |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 144 | |
| 145 | /*----------------------------------------------------------------------- |
| 146 | * Cache Configuration |
| 147 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 148 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 149 | |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 150 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 151 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 152 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 153 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
TsiChung Liew | dd9f054 | 2010-03-11 22:12:53 -0600 | [diff] [blame] | 154 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) |
| 155 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ |
| 156 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 157 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 158 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ |
| 159 | CF_CACR_CEIB | CF_CACR_DBWE | \ |
| 160 | CF_CACR_EUSP) |
| 161 | |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 162 | /*----------------------------------------------------------------------- |
| 163 | * Memory bank definitions |
| 164 | */ |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 165 | #define CONFIG_SYS_CS0_BASE 0xFFE00000 |
| 166 | #define CONFIG_SYS_CS0_CTRL 0x00001980 |
| 167 | #define CONFIG_SYS_CS0_MASK 0x001F0001 |
| 168 | |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 169 | /*----------------------------------------------------------------------- |
| 170 | * Port configuration |
| 171 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 172 | #define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ |
| 173 | #define CONFIG_SYS_PADDR 0x0000000 |
| 174 | #define CONFIG_SYS_PADAT 0x0000000 |
wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 175 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 176 | #define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ |
| 177 | #define CONFIG_SYS_PBDDR 0x0000000 |
| 178 | #define CONFIG_SYS_PBDAT 0x0000000 |
wdenk | 4e5ca3e | 2003-12-08 01:34:36 +0000 | [diff] [blame] | 179 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 180 | #define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ |
| 181 | #define CONFIG_SYS_PCDDR 0x0000000 |
| 182 | #define CONFIG_SYS_PCDAT 0x0000000 |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 183 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 184 | #define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ |
| 185 | #define CONFIG_SYS_PCDDR 0x0000000 |
| 186 | #define CONFIG_SYS_PCDAT 0x0000000 |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 187 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 188 | #define CONFIG_SYS_PEHLPAR 0xC0 |
| 189 | #define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ |
| 190 | #define CONFIG_SYS_DDRUA 0x05 |
| 191 | #define CONFIG_SYS_PJPAR 0xFF |
TsiChungLiew | f28e1bd | 2007-08-15 20:32:06 -0500 | [diff] [blame] | 192 | |
| 193 | #endif /* _CONFIG_M5282EVB_H */ |