Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / cb9843bda3e500eb4add1927be4ed72077a69774 / . / include / configs / ethernut5.h
blob: 2126731ccfc90c2724e0ebc9414194fe709f0103 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]2/*
3 * (C) Copyright 2011
4 * egnite GmbH <info@egnite.de>
5 *
6 * Configuation settings for Ethernut 5 with AT91SAM9XE.
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <asm/hardware.h>
13
14/* The first stage boot loader expects u-boot running at this address. */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]15
16/* The first stage boot loader takes care of low level initialization. */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]17
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]18/* CPU information */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]19
20/* ARM asynchronous clock */
21#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
22#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]23
24/* 32kB internal SRAM */
Tom Rinieaf6ea62022-05-25 12:16:03 -0400[diff] [blame]25#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 /*AT91SAM9XE_SRAM_BASE */
26#define CONFIG_SYS_INIT_RAM_SIZE (32 << 10)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]27
28/* 128MB SDRAM in 1 bank */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]29#define CONFIG_SYS_SDRAM_BASE 0x20000000
30#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]31
32/* 512kB on-chip NOR flash */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]33# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]34# define CONFIG_SYS_MAX_FLASH_SECT 32
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]35
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]36
Wenyou.Yang@microchip.com94db5122017-07-21 14:30:57 +0800[diff] [blame]37/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]38
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]39/* NAND flash */
40#ifdef CONFIG_CMD_NAND
41#define CONFIG_SYS_MAX_NAND_DEVICE 1
42#define CONFIG_SYS_NAND_BASE 0x40000000
43#define CONFIG_SYS_NAND_DBW_8
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]44/* our ALE is AD21 */
45#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
46/* our CLE is AD22 */
47#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmannac45bb12013-11-29 12:13:45 +0100[diff] [blame]48#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]49#endif
50
51/* JFFS2 */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]52
53/* Ethernet */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]54#define CONFIG_PHY_ID 0
55#define CONFIG_MACB_SEARCH_PHY
56
57/* MMC */
58#ifdef CONFIG_CMD_MMC
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]59#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
60#endif
61
62/* USB */
63#ifdef CONFIG_CMD_USB
64#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800[diff] [blame]65#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]66#define CONFIG_USB_OHCI_NEW
67#define CONFIG_SYS_USB_OHCI_CPU_INIT
68#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
69#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
70#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]71#endif
72
73/* RTC */
74#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]75#define CONFIG_SYS_I2C_RTC_ADDR 0x51
76#endif
77
78/* I2C */
79#define CONFIG_SYS_MAX_I2C_BUS 1
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]80
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]81#define I2C_SOFT_DECLARATIONS
82
83#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
84#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
85
86#define I2C_INIT { \
87 at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
88 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
89 at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
90 at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
91 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
92}
93
94#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
95#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
96#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
97#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
98#define I2C_DELAY udelay(100)
99#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
100
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]101/* File systems */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]102
103/* Boot command */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]104
105/* Misc. u-boot settings */
Tim Schendekehl14c32612011-11-01 23:55:01 +0000[diff] [blame]106
107#endif