blob: 44b6268ae32670a3c6d8a02c696cae7cdca0e8db [file] [log] [blame]
Tom Rini1480fdf2015-07-31 19:55:08 -04001/*
2 * Device Tree Source for AM33xx clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&scm_clocks {
Felix Brackfdce9d32018-12-05 14:53:42 +010011 sys_clkin_ck: sys_clkin_ck@40 {
Tom Rini1480fdf2015-07-31 19:55:08 -040012 #clock-cells = <0>;
13 compatible = "ti,mux-clock";
14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
15 ti,bit-shift = <22>;
16 reg = <0x0040>;
17 };
18
19 adc_tsc_fck: adc_tsc_fck {
20 #clock-cells = <0>;
21 compatible = "fixed-factor-clock";
22 clocks = <&sys_clkin_ck>;
23 clock-mult = <1>;
24 clock-div = <1>;
25 };
26
27 dcan0_fck: dcan0_fck {
28 #clock-cells = <0>;
29 compatible = "fixed-factor-clock";
30 clocks = <&sys_clkin_ck>;
31 clock-mult = <1>;
32 clock-div = <1>;
33 };
34
35 dcan1_fck: dcan1_fck {
36 #clock-cells = <0>;
37 compatible = "fixed-factor-clock";
38 clocks = <&sys_clkin_ck>;
39 clock-mult = <1>;
40 clock-div = <1>;
41 };
42
43 mcasp0_fck: mcasp0_fck {
44 #clock-cells = <0>;
45 compatible = "fixed-factor-clock";
46 clocks = <&sys_clkin_ck>;
47 clock-mult = <1>;
48 clock-div = <1>;
49 };
50
51 mcasp1_fck: mcasp1_fck {
52 #clock-cells = <0>;
53 compatible = "fixed-factor-clock";
54 clocks = <&sys_clkin_ck>;
55 clock-mult = <1>;
56 clock-div = <1>;
57 };
58
59 smartreflex0_fck: smartreflex0_fck {
60 #clock-cells = <0>;
61 compatible = "fixed-factor-clock";
62 clocks = <&sys_clkin_ck>;
63 clock-mult = <1>;
64 clock-div = <1>;
65 };
66
67 smartreflex1_fck: smartreflex1_fck {
68 #clock-cells = <0>;
69 compatible = "fixed-factor-clock";
70 clocks = <&sys_clkin_ck>;
71 clock-mult = <1>;
72 clock-div = <1>;
73 };
74
75 sha0_fck: sha0_fck {
76 #clock-cells = <0>;
77 compatible = "fixed-factor-clock";
78 clocks = <&sys_clkin_ck>;
79 clock-mult = <1>;
80 clock-div = <1>;
81 };
82
83 aes0_fck: aes0_fck {
84 #clock-cells = <0>;
85 compatible = "fixed-factor-clock";
86 clocks = <&sys_clkin_ck>;
87 clock-mult = <1>;
88 clock-div = <1>;
89 };
90
91 rng_fck: rng_fck {
92 #clock-cells = <0>;
93 compatible = "fixed-factor-clock";
94 clocks = <&sys_clkin_ck>;
95 clock-mult = <1>;
96 clock-div = <1>;
97 };
98
99 ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
100 #clock-cells = <0>;
101 compatible = "ti,gate-clock";
102 clocks = <&l4ls_gclk>;
103 ti,bit-shift = <0>;
104 reg = <0x0664>;
105 };
106
107 ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
108 #clock-cells = <0>;
109 compatible = "ti,gate-clock";
110 clocks = <&l4ls_gclk>;
111 ti,bit-shift = <1>;
112 reg = <0x0664>;
113 };
114
115 ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
116 #clock-cells = <0>;
117 compatible = "ti,gate-clock";
118 clocks = <&l4ls_gclk>;
119 ti,bit-shift = <2>;
120 reg = <0x0664>;
121 };
122};
123&prcm_clocks {
124 clk_32768_ck: clk_32768_ck {
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
127 clock-frequency = <32768>;
128 };
129
130 clk_rc32k_ck: clk_rc32k_ck {
131 #clock-cells = <0>;
132 compatible = "fixed-clock";
133 clock-frequency = <32000>;
134 };
135
136 virt_19200000_ck: virt_19200000_ck {
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
139 clock-frequency = <19200000>;
140 };
141
142 virt_24000000_ck: virt_24000000_ck {
143 #clock-cells = <0>;
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 };
147
148 virt_25000000_ck: virt_25000000_ck {
149 #clock-cells = <0>;
150 compatible = "fixed-clock";
151 clock-frequency = <25000000>;
152 };
153
154 virt_26000000_ck: virt_26000000_ck {
155 #clock-cells = <0>;
156 compatible = "fixed-clock";
157 clock-frequency = <26000000>;
158 };
159
160 tclkin_ck: tclkin_ck {
161 #clock-cells = <0>;
162 compatible = "fixed-clock";
163 clock-frequency = <12000000>;
164 };
165
Felix Brackfdce9d32018-12-05 14:53:42 +0100166 dpll_core_ck: dpll_core_ck@490 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400167 #clock-cells = <0>;
168 compatible = "ti,am3-dpll-core-clock";
169 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
Dario Binacchibf4a54f2021-09-26 11:58:56 +0200170 reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400171 };
172
173 dpll_core_x2_ck: dpll_core_x2_ck {
174 #clock-cells = <0>;
175 compatible = "ti,am3-dpll-x2-clock";
176 clocks = <&dpll_core_ck>;
177 };
178
Felix Brackfdce9d32018-12-05 14:53:42 +0100179 dpll_core_m4_ck: dpll_core_m4_ck@480 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400180 #clock-cells = <0>;
181 compatible = "ti,divider-clock";
182 clocks = <&dpll_core_x2_ck>;
183 ti,max-div = <31>;
184 reg = <0x0480>;
185 ti,index-starts-at-one;
186 };
187
Felix Brackfdce9d32018-12-05 14:53:42 +0100188 dpll_core_m5_ck: dpll_core_m5_ck@484 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400189 #clock-cells = <0>;
190 compatible = "ti,divider-clock";
191 clocks = <&dpll_core_x2_ck>;
192 ti,max-div = <31>;
193 reg = <0x0484>;
194 ti,index-starts-at-one;
195 };
196
Felix Brackfdce9d32018-12-05 14:53:42 +0100197 dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400198 #clock-cells = <0>;
199 compatible = "ti,divider-clock";
200 clocks = <&dpll_core_x2_ck>;
201 ti,max-div = <31>;
202 reg = <0x04d8>;
203 ti,index-starts-at-one;
204 };
205
Felix Brackfdce9d32018-12-05 14:53:42 +0100206 dpll_mpu_ck: dpll_mpu_ck@488 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400207 #clock-cells = <0>;
208 compatible = "ti,am3-dpll-clock";
209 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
Dario Binacchibf4a54f2021-09-26 11:58:56 +0200210 reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400211 };
212
Felix Brackfdce9d32018-12-05 14:53:42 +0100213 dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400214 #clock-cells = <0>;
215 compatible = "ti,divider-clock";
216 clocks = <&dpll_mpu_ck>;
217 ti,max-div = <31>;
218 reg = <0x04a8>;
219 ti,index-starts-at-one;
220 };
221
Felix Brackfdce9d32018-12-05 14:53:42 +0100222 dpll_ddr_ck: dpll_ddr_ck@494 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400223 #clock-cells = <0>;
224 compatible = "ti,am3-dpll-no-gate-clock";
225 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
Dario Binacchibf4a54f2021-09-26 11:58:56 +0200226 reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400227 };
228
Felix Brackfdce9d32018-12-05 14:53:42 +0100229 dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400230 #clock-cells = <0>;
231 compatible = "ti,divider-clock";
232 clocks = <&dpll_ddr_ck>;
233 ti,max-div = <31>;
234 reg = <0x04a0>;
235 ti,index-starts-at-one;
236 };
237
238 dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
239 #clock-cells = <0>;
240 compatible = "fixed-factor-clock";
241 clocks = <&dpll_ddr_m2_ck>;
242 clock-mult = <1>;
243 clock-div = <2>;
244 };
245
Felix Brackfdce9d32018-12-05 14:53:42 +0100246 dpll_disp_ck: dpll_disp_ck@498 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400247 #clock-cells = <0>;
248 compatible = "ti,am3-dpll-no-gate-clock";
249 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
Dario Binacchibf4a54f2021-09-26 11:58:56 +0200250 reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400251 };
252
Felix Brackfdce9d32018-12-05 14:53:42 +0100253 dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400254 #clock-cells = <0>;
255 compatible = "ti,divider-clock";
256 clocks = <&dpll_disp_ck>;
257 ti,max-div = <31>;
258 reg = <0x04a4>;
259 ti,index-starts-at-one;
260 ti,set-rate-parent;
261 };
262
Felix Brackfdce9d32018-12-05 14:53:42 +0100263 dpll_per_ck: dpll_per_ck@48c {
Tom Rini1480fdf2015-07-31 19:55:08 -0400264 #clock-cells = <0>;
265 compatible = "ti,am3-dpll-no-gate-j-type-clock";
266 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
Dario Binacchibf4a54f2021-09-26 11:58:56 +0200267 reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400268 };
269
Felix Brackfdce9d32018-12-05 14:53:42 +0100270 dpll_per_m2_ck: dpll_per_m2_ck@4ac {
Tom Rini1480fdf2015-07-31 19:55:08 -0400271 #clock-cells = <0>;
272 compatible = "ti,divider-clock";
273 clocks = <&dpll_per_ck>;
274 ti,max-div = <31>;
275 reg = <0x04ac>;
276 ti,index-starts-at-one;
277 };
278
279 dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
280 #clock-cells = <0>;
281 compatible = "fixed-factor-clock";
282 clocks = <&dpll_per_m2_ck>;
283 clock-mult = <1>;
284 clock-div = <4>;
285 };
286
287 dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
288 #clock-cells = <0>;
289 compatible = "fixed-factor-clock";
290 clocks = <&dpll_per_m2_ck>;
291 clock-mult = <1>;
292 clock-div = <4>;
293 };
294
Tom Rini1480fdf2015-07-31 19:55:08 -0400295 clk_24mhz: clk_24mhz {
296 #clock-cells = <0>;
297 compatible = "fixed-factor-clock";
298 clocks = <&dpll_per_m2_ck>;
299 clock-mult = <1>;
300 clock-div = <8>;
301 };
302
303 clkdiv32k_ck: clkdiv32k_ck {
304 #clock-cells = <0>;
305 compatible = "fixed-factor-clock";
306 clocks = <&clk_24mhz>;
307 clock-mult = <1>;
308 clock-div = <732>;
309 };
310
Tom Rini1480fdf2015-07-31 19:55:08 -0400311 l3_gclk: l3_gclk {
312 #clock-cells = <0>;
313 compatible = "fixed-factor-clock";
314 clocks = <&dpll_core_m4_ck>;
315 clock-mult = <1>;
316 clock-div = <1>;
317 };
318
Felix Brackfdce9d32018-12-05 14:53:42 +0100319 pruss_ocp_gclk: pruss_ocp_gclk@530 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400320 #clock-cells = <0>;
321 compatible = "ti,mux-clock";
322 clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
323 reg = <0x0530>;
324 };
325
Felix Brackfdce9d32018-12-05 14:53:42 +0100326 mmu_fck: mmu_fck@914 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400327 #clock-cells = <0>;
328 compatible = "ti,gate-clock";
329 clocks = <&dpll_core_m4_ck>;
330 ti,bit-shift = <1>;
331 reg = <0x0914>;
332 };
333
Felix Brackfdce9d32018-12-05 14:53:42 +0100334 timer1_fck: timer1_fck@528 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400335 #clock-cells = <0>;
336 compatible = "ti,mux-clock";
Dario Binacchi6337d532020-12-30 00:06:30 +0100337 clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400338 reg = <0x0528>;
339 };
340
Felix Brackfdce9d32018-12-05 14:53:42 +0100341 timer2_fck: timer2_fck@508 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400342 #clock-cells = <0>;
343 compatible = "ti,mux-clock";
Dario Binacchi6337d532020-12-30 00:06:30 +0100344 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400345 reg = <0x0508>;
346 };
347
Felix Brackfdce9d32018-12-05 14:53:42 +0100348 timer3_fck: timer3_fck@50c {
Tom Rini1480fdf2015-07-31 19:55:08 -0400349 #clock-cells = <0>;
350 compatible = "ti,mux-clock";
Dario Binacchi6337d532020-12-30 00:06:30 +0100351 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400352 reg = <0x050c>;
353 };
354
Felix Brackfdce9d32018-12-05 14:53:42 +0100355 timer4_fck: timer4_fck@510 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400356 #clock-cells = <0>;
357 compatible = "ti,mux-clock";
Dario Binacchi6337d532020-12-30 00:06:30 +0100358 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400359 reg = <0x0510>;
360 };
361
Felix Brackfdce9d32018-12-05 14:53:42 +0100362 timer5_fck: timer5_fck@518 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400363 #clock-cells = <0>;
364 compatible = "ti,mux-clock";
Dario Binacchi6337d532020-12-30 00:06:30 +0100365 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400366 reg = <0x0518>;
367 };
368
Felix Brackfdce9d32018-12-05 14:53:42 +0100369 timer6_fck: timer6_fck@51c {
Tom Rini1480fdf2015-07-31 19:55:08 -0400370 #clock-cells = <0>;
371 compatible = "ti,mux-clock";
Dario Binacchi6337d532020-12-30 00:06:30 +0100372 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400373 reg = <0x051c>;
374 };
375
Felix Brackfdce9d32018-12-05 14:53:42 +0100376 timer7_fck: timer7_fck@504 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400377 #clock-cells = <0>;
378 compatible = "ti,mux-clock";
Dario Binacchi6337d532020-12-30 00:06:30 +0100379 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400380 reg = <0x0504>;
381 };
382
Felix Brackfdce9d32018-12-05 14:53:42 +0100383 usbotg_fck: usbotg_fck@47c {
Tom Rini1480fdf2015-07-31 19:55:08 -0400384 #clock-cells = <0>;
385 compatible = "ti,gate-clock";
386 clocks = <&dpll_per_ck>;
387 ti,bit-shift = <8>;
388 reg = <0x047c>;
389 };
390
391 dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
392 #clock-cells = <0>;
393 compatible = "fixed-factor-clock";
394 clocks = <&dpll_core_m4_ck>;
395 clock-mult = <1>;
396 clock-div = <2>;
397 };
398
Felix Brackfdce9d32018-12-05 14:53:42 +0100399 ieee5000_fck: ieee5000_fck@e4 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400400 #clock-cells = <0>;
401 compatible = "ti,gate-clock";
402 clocks = <&dpll_core_m4_div2_ck>;
403 ti,bit-shift = <1>;
404 reg = <0x00e4>;
405 };
406
Felix Brackfdce9d32018-12-05 14:53:42 +0100407 wdt1_fck: wdt1_fck@538 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400408 #clock-cells = <0>;
409 compatible = "ti,mux-clock";
Dario Binacchi6337d532020-12-30 00:06:30 +0100410 clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400411 reg = <0x0538>;
412 };
413
414 l4_rtc_gclk: l4_rtc_gclk {
415 #clock-cells = <0>;
416 compatible = "fixed-factor-clock";
417 clocks = <&dpll_core_m4_ck>;
418 clock-mult = <1>;
419 clock-div = <2>;
420 };
421
422 l4hs_gclk: l4hs_gclk {
423 #clock-cells = <0>;
424 compatible = "fixed-factor-clock";
425 clocks = <&dpll_core_m4_ck>;
426 clock-mult = <1>;
427 clock-div = <1>;
428 };
429
430 l3s_gclk: l3s_gclk {
431 #clock-cells = <0>;
432 compatible = "fixed-factor-clock";
433 clocks = <&dpll_core_m4_div2_ck>;
434 clock-mult = <1>;
435 clock-div = <1>;
436 };
437
438 l4fw_gclk: l4fw_gclk {
439 #clock-cells = <0>;
440 compatible = "fixed-factor-clock";
441 clocks = <&dpll_core_m4_div2_ck>;
442 clock-mult = <1>;
443 clock-div = <1>;
444 };
445
446 l4ls_gclk: l4ls_gclk {
447 #clock-cells = <0>;
448 compatible = "fixed-factor-clock";
449 clocks = <&dpll_core_m4_div2_ck>;
450 clock-mult = <1>;
451 clock-div = <1>;
452 };
453
454 sysclk_div_ck: sysclk_div_ck {
455 #clock-cells = <0>;
456 compatible = "fixed-factor-clock";
457 clocks = <&dpll_core_m4_ck>;
458 clock-mult = <1>;
459 clock-div = <1>;
460 };
461
462 cpsw_125mhz_gclk: cpsw_125mhz_gclk {
463 #clock-cells = <0>;
464 compatible = "fixed-factor-clock";
465 clocks = <&dpll_core_m5_ck>;
466 clock-mult = <1>;
467 clock-div = <2>;
468 };
469
Felix Brackfdce9d32018-12-05 14:53:42 +0100470 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400471 #clock-cells = <0>;
472 compatible = "ti,mux-clock";
473 clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
474 reg = <0x0520>;
475 };
476
Felix Brackfdce9d32018-12-05 14:53:42 +0100477 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
Tom Rini1480fdf2015-07-31 19:55:08 -0400478 #clock-cells = <0>;
479 compatible = "ti,mux-clock";
Dario Binacchi6337d532020-12-30 00:06:30 +0100480 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
Tom Rini1480fdf2015-07-31 19:55:08 -0400481 reg = <0x053c>;
482 };
483
Felix Brackfdce9d32018-12-05 14:53:42 +0100484 lcd_gclk: lcd_gclk@534 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400485 #clock-cells = <0>;
486 compatible = "ti,mux-clock";
487 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
488 reg = <0x0534>;
489 ti,set-rate-parent;
490 };
491
492 mmc_clk: mmc_clk {
493 #clock-cells = <0>;
494 compatible = "fixed-factor-clock";
495 clocks = <&dpll_per_m2_ck>;
496 clock-mult = <1>;
497 clock-div = <2>;
498 };
499
Felix Brackfdce9d32018-12-05 14:53:42 +0100500 gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
Tom Rini1480fdf2015-07-31 19:55:08 -0400501 #clock-cells = <0>;
502 compatible = "ti,mux-clock";
503 clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
504 ti,bit-shift = <1>;
505 reg = <0x052c>;
506 };
507
Felix Brackfdce9d32018-12-05 14:53:42 +0100508 gfx_fck_div_ck: gfx_fck_div_ck@52c {
Tom Rini1480fdf2015-07-31 19:55:08 -0400509 #clock-cells = <0>;
510 compatible = "ti,divider-clock";
511 clocks = <&gfx_fclk_clksel_ck>;
512 reg = <0x052c>;
513 ti,max-div = <2>;
514 };
515
Felix Brackfdce9d32018-12-05 14:53:42 +0100516 sysclkout_pre_ck: sysclkout_pre_ck@700 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400517 #clock-cells = <0>;
518 compatible = "ti,mux-clock";
519 clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
520 reg = <0x0700>;
521 };
522
Felix Brackfdce9d32018-12-05 14:53:42 +0100523 clkout2_div_ck: clkout2_div_ck@700 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400524 #clock-cells = <0>;
525 compatible = "ti,divider-clock";
526 clocks = <&sysclkout_pre_ck>;
527 ti,bit-shift = <3>;
528 ti,max-div = <8>;
529 reg = <0x0700>;
530 };
531
Felix Brackfdce9d32018-12-05 14:53:42 +0100532 clkout2_ck: clkout2_ck@700 {
Tom Rini1480fdf2015-07-31 19:55:08 -0400533 #clock-cells = <0>;
534 compatible = "ti,gate-clock";
535 clocks = <&clkout2_div_ck>;
536 ti,bit-shift = <7>;
537 reg = <0x0700>;
538 };
539};
540
Felix Brackfdce9d32018-12-05 14:53:42 +0100541&prcm {
Dario Binacchi252ee3c2021-02-13 12:09:19 +0100542 per_cm: per-cm@0 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100543 compatible = "ti,omap4-cm";
Dario Binacchi6337d532020-12-30 00:06:30 +0100544 reg = <0x0 0x400>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100545 #address-cells = <1>;
546 #size-cells = <1>;
Dario Binacchi6337d532020-12-30 00:06:30 +0100547 ranges = <0 0x0 0x400>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100548
Dario Binacchi6337d532020-12-30 00:06:30 +0100549 l4ls_clkctrl: l4ls-clkctrl@38 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100550 compatible = "ti,clkctrl";
Dario Binacchi6337d532020-12-30 00:06:30 +0100551 reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
552 #clock-cells = <2>;
553 };
554
555 l3s_clkctrl: l3s-clkctrl@1c {
556 compatible = "ti,clkctrl";
557 reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
558 #clock-cells = <2>;
559 };
560
561 l3_clkctrl: l3-clkctrl@24 {
562 compatible = "ti,clkctrl";
563 reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
564 #clock-cells = <2>;
565 };
566
567 l4hs_clkctrl: l4hs-clkctrl@120 {
568 compatible = "ti,clkctrl";
569 reg = <0x120 0x4>;
570 #clock-cells = <2>;
571 };
572
573 pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
574 compatible = "ti,clkctrl";
575 reg = <0xe8 0x4>;
576 #clock-cells = <2>;
577 };
578
579 cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
580 compatible = "ti,clkctrl";
581 reg = <0x0 0x18>;
582 #clock-cells = <2>;
583 };
584
585 lcdc_clkctrl: lcdc-clkctrl@18 {
586 compatible = "ti,clkctrl";
587 reg = <0x18 0x4>;
588 #clock-cells = <2>;
589 };
590
591 clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
592 compatible = "ti,clkctrl";
593 reg = <0x14c 0x4>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100594 #clock-cells = <2>;
595 };
596 };
597
Dario Binacchi6337d532020-12-30 00:06:30 +0100598 wkup_cm: wkup-cm@400 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100599 compatible = "ti,omap4-cm";
600 reg = <0x400 0x100>;
601 #address-cells = <1>;
602 #size-cells = <1>;
603 ranges = <0 0x400 0x100>;
604
Dario Binacchi6337d532020-12-30 00:06:30 +0100605 l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100606 compatible = "ti,clkctrl";
Dario Binacchif43d9e92021-02-13 12:00:45 +0100607 reg = <0x0 0x10>, <0xb4 0x24>;
Dario Binacchi6337d532020-12-30 00:06:30 +0100608 #clock-cells = <2>;
609 };
610
611 l3_aon_clkctrl: l3-aon-clkctrl@14 {
612 compatible = "ti,clkctrl";
613 reg = <0x14 0x4>;
614 #clock-cells = <2>;
615 };
616
617 l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
618 compatible = "ti,clkctrl";
619 reg = <0xb0 0x4>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100620 #clock-cells = <2>;
621 };
622 };
623
Dario Binacchi6337d532020-12-30 00:06:30 +0100624 mpu_cm: mpu-cm@600 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100625 compatible = "ti,omap4-cm";
626 reg = <0x600 0x100>;
627 #address-cells = <1>;
628 #size-cells = <1>;
629 ranges = <0 0x600 0x100>;
630
Dario Binacchi6337d532020-12-30 00:06:30 +0100631 mpu_clkctrl: mpu-clkctrl@0 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100632 compatible = "ti,clkctrl";
Dario Binacchi6337d532020-12-30 00:06:30 +0100633 reg = <0x0 0x8>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100634 #clock-cells = <2>;
635 };
636 };
637
Dario Binacchi6337d532020-12-30 00:06:30 +0100638 l4_rtc_cm: l4-rtc-cm@800 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100639 compatible = "ti,omap4-cm";
640 reg = <0x800 0x100>;
641 #address-cells = <1>;
642 #size-cells = <1>;
643 ranges = <0 0x800 0x100>;
644
Dario Binacchi6337d532020-12-30 00:06:30 +0100645 l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100646 compatible = "ti,clkctrl";
647 reg = <0x0 0x4>;
648 #clock-cells = <2>;
649 };
650 };
651
Dario Binacchi6337d532020-12-30 00:06:30 +0100652 gfx_l3_cm: gfx-l3-cm@900 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100653 compatible = "ti,omap4-cm";
654 reg = <0x900 0x100>;
655 #address-cells = <1>;
656 #size-cells = <1>;
657 ranges = <0 0x900 0x100>;
658
Dario Binacchi6337d532020-12-30 00:06:30 +0100659 gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100660 compatible = "ti,clkctrl";
Dario Binacchi6337d532020-12-30 00:06:30 +0100661 reg = <0x0 0x8>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100662 #clock-cells = <2>;
663 };
664 };
665
Dario Binacchi6337d532020-12-30 00:06:30 +0100666 l4_cefuse_cm: l4-cefuse-cm@a00 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100667 compatible = "ti,omap4-cm";
668 reg = <0xa00 0x100>;
669 #address-cells = <1>;
670 #size-cells = <1>;
671 ranges = <0 0xa00 0x100>;
672
Dario Binacchi252ee3c2021-02-13 12:09:19 +0100673 l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
Felix Brackfdce9d32018-12-05 14:53:42 +0100674 compatible = "ti,clkctrl";
Dario Binacchi252ee3c2021-02-13 12:09:19 +0100675 reg = <0x0 0x24>;
Felix Brackfdce9d32018-12-05 14:53:42 +0100676 #clock-cells = <2>;
677 };
Tom Rini1480fdf2015-07-31 19:55:08 -0400678 };
679};