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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Igor Grinbergb09bf722014-11-05 14:25:35 +02002/*
3 * (C) Copyright 2013 CompuLab, Ltd.
4 * Author: Igor Grinberg <grinberg@compulab.co.il>
5 *
6 * Configuration settings for the CompuLab CM-T3517 board
Igor Grinbergb09bf722014-11-05 14:25:35 +02007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Configuration Options
14 */
Igor Grinbergb09bf722014-11-05 14:25:35 +020015#define CONFIG_CM_T3517 /* working with CM-T3517 */
Igor Grinbergb09bf722014-11-05 14:25:35 +020016
Igor Grinbergb09bf722014-11-05 14:25:35 +020017/*
18 * This is needed for the DMA stuff.
19 * Although the default iss 64, we still define it
20 * to be on the safe side once the default is changed.
21 */
Igor Grinbergb09bf722014-11-05 14:25:35 +020022
Igor Grinbergb09bf722014-11-05 14:25:35 +020023#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menon987ec582015-03-09 17:12:04 -050024#include <asm/arch/omap.h>
Igor Grinbergb09bf722014-11-05 14:25:35 +020025
Dmitry Lifshitzf3b44e82015-09-09 11:27:17 +030026#define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517
27
Igor Grinbergb09bf722014-11-05 14:25:35 +020028/* Clock Defines */
29#define V_OSCK 26000000 /* Clock output from T2 */
30#define V_SCLK (V_OSCK >> 1)
31
Igor Grinbergb09bf722014-11-05 14:25:35 +020032/*
33 * The early kernel mapping on ARM currently only maps from the base of DRAM
34 * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
35 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
36 * so that leaves DRAM base to DRAM base + 0x4000 available.
37 */
38#define CONFIG_SYS_BOOTMAPSZ 0x4000
39
40#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
41#define CONFIG_SETUP_MEMORY_TAGS
42#define CONFIG_INITRD_TAG
43#define CONFIG_REVISION_TAG
44#define CONFIG_SERIAL_TAG
45
46/*
47 * Size of malloc() pool
48 */
Dmitry Lifshitz2f6e4bf2015-09-09 11:25:39 +030049#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Igor Grinbergb09bf722014-11-05 14:25:35 +020050#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
51
52/*
53 * Hardware drivers
54 */
55
56/*
57 * NS16550 Configuration
58 */
Igor Grinbergb09bf722014-11-05 14:25:35 +020059#define CONFIG_SYS_NS16550_SERIAL
60#define CONFIG_SYS_NS16550_REG_SIZE (-4)
61#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
62
63/*
64 * select serial console configuration
65 */
Igor Grinbergb09bf722014-11-05 14:25:35 +020066#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
67#define CONFIG_SERIAL3 3 /* UART3 */
Igor Grinbergb09bf722014-11-05 14:25:35 +020068
69/* allow to overwrite serial and ethaddr */
70#define CONFIG_ENV_OVERWRITE
Igor Grinbergb09bf722014-11-05 14:25:35 +020071#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
72 115200}
73
Igor Grinberg011f5c12014-11-03 11:32:25 +020074/* USB */
Igor Grinberg011f5c12014-11-03 11:32:25 +020075
76#ifndef CONFIG_USB_MUSB_AM35X
Igor Grinberg011f5c12014-11-03 11:32:25 +020077#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
78#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
Igor Grinberg011f5c12014-11-03 11:32:25 +020079#endif /* CONFIG_USB_MUSB_AM35X */
80
Igor Grinbergb09bf722014-11-05 14:25:35 +020081/* commands to include */
Igor Grinbergb09bf722014-11-05 14:25:35 +020082
Igor Grinbergb09bf722014-11-05 14:25:35 +020083#define CONFIG_SYS_I2C
Igor Grinbergb09bf722014-11-05 14:25:35 +020084#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
85#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
86#define CONFIG_SYS_I2C_EEPROM_BUS 0
87#define CONFIG_I2C_MULTI_BUS
88
89/*
90 * Board NAND Info.
91 */
Igor Grinbergb09bf722014-11-05 14:25:35 +020092#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
93 /* to access nand at */
94 /* CS0 */
95#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
96 /* devices */
97
98/* Environment information */
Igor Grinbergb09bf722014-11-05 14:25:35 +020099#define CONFIG_EXTRA_ENV_SETTINGS \
100 "loadaddr=0x82000000\0" \
101 "baudrate=115200\0" \
102 "console=ttyO2,115200n8\0" \
Dmitry Lifshitze093d0b2015-09-08 09:50:00 +0300103 "netretry=yes\0" \
Igor Grinbergb09bf722014-11-05 14:25:35 +0200104 "mpurate=auto\0" \
105 "vram=12M\0" \
106 "dvimode=1024x768MR-16@60\0" \
107 "defaultdisplay=dvi\0" \
108 "mmcdev=0\0" \
109 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
110 "mmcrootfstype=ext4\0" \
111 "nandroot=/dev/mtdblock4 rw\0" \
112 "nandrootfstype=ubifs\0" \
113 "mmcargs=setenv bootargs console=${console} " \
114 "mpurate=${mpurate} " \
115 "vram=${vram} " \
116 "omapfb.mode=dvi:${dvimode} " \
117 "omapdss.def_disp=${defaultdisplay} " \
118 "root=${mmcroot} " \
119 "rootfstype=${mmcrootfstype}\0" \
120 "nandargs=setenv bootargs console=${console} " \
121 "mpurate=${mpurate} " \
122 "vram=${vram} " \
123 "omapfb.mode=dvi:${dvimode} " \
124 "omapdss.def_disp=${defaultdisplay} " \
125 "root=${nandroot} " \
126 "rootfstype=${nandrootfstype}\0" \
127 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
128 "bootscript=echo Running bootscript from mmc ...; " \
129 "source ${loadaddr}\0" \
130 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
131 "mmcboot=echo Booting from mmc ...; " \
132 "run mmcargs; " \
133 "bootm ${loadaddr}\0" \
134 "nandboot=echo Booting from nand ...; " \
135 "run nandargs; " \
136 "nand read ${loadaddr} 2a0000 400000; " \
137 "bootm ${loadaddr}\0" \
138
Igor Grinbergb09bf722014-11-05 14:25:35 +0200139#define CONFIG_BOOTCOMMAND \
140 "mmc dev ${mmcdev}; if mmc rescan; then " \
141 "if run loadbootscript; then " \
142 "run bootscript; " \
143 "else " \
144 "if run loaduimage; then " \
145 "run mmcboot; " \
146 "else run nandboot; " \
147 "fi; " \
148 "fi; " \
149 "else run nandboot; fi"
150
151/*
152 * Miscellaneous configurable options
153 */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200154#define CONFIG_TIMESTAMP
155#define CONFIG_SYS_AUTOLOAD "no"
Igor Grinbergb09bf722014-11-05 14:25:35 +0200156#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200157#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200158
159#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
160
161/*
162 * AM3517 has 12 GP timers, they can be driven by the system clock
163 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
164 * This rate is divided by a local divisor.
165 */
166#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
167#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
168#define CONFIG_SYS_HZ 1000
169
170/*-----------------------------------------------------------------------
171 * Physical Memory Map
172 */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200173#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
174#define CONFIG_SYS_CS0_SIZE (256 << 20)
175
176/*-----------------------------------------------------------------------
177 * FLASH and environment organization
178 */
179
180/* **** PISMO SUPPORT *** */
181/* Monitor at start of flash */
182#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
183#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
184
Adam Ford7672d9d2017-09-04 21:08:02 -0500185#define CONFIG_ENV_OFFSET 0x260000
186#define CONFIG_ENV_ADDR 0x260000
Igor Grinbergb09bf722014-11-05 14:25:35 +0200187
Igor Grinberga8a78c72014-11-03 11:32:26 +0200188#if defined(CONFIG_CMD_NET)
Igor Grinberga8a78c72014-11-03 11:32:26 +0200189#define CONFIG_DRIVER_TI_EMAC_USE_RMII
Dmitry Lifshitze093d0b2015-09-08 09:50:00 +0300190#define CONFIG_ARP_TIMEOUT 200UL
191#define CONFIG_NET_RETRY_COUNT 5
Igor Grinberga8a78c72014-11-03 11:32:26 +0200192#endif /* CONFIG_CMD_NET */
193
Igor Grinbergb09bf722014-11-05 14:25:35 +0200194/* additions for new relocation code, must be added to all boards */
195#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
196#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
197#define CONFIG_SYS_INIT_RAM_SIZE 0x800
198#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
199 CONFIG_SYS_INIT_RAM_SIZE - \
200 GENERATED_GBL_DATA_SIZE)
201
202/* Status LED */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200203#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
Igor Grinbergb09bf722014-11-05 14:25:35 +0200204
Igor Grinberg40bbd522014-11-03 11:32:27 +0200205/* Display Configuration */
Igor Grinberg40bbd522014-11-03 11:32:27 +0200206#define LCD_BPP LCD_COLOR16
207
Igor Grinberg40bbd522014-11-03 11:32:27 +0200208#define CONFIG_SPLASH_SCREEN
209#define CONFIG_SPLASHIMAGE_GUARD
Igor Grinberg40bbd522014-11-03 11:32:27 +0200210#define CONFIG_BMP_16BPP
211#define CONFIG_SCF0403_LCD
212
Nikita Kiryanov19a90ed2016-04-16 17:55:08 +0300213/* EEPROM */
Nikita Kiryanov19a90ed2016-04-16 17:55:08 +0300214#define CONFIG_ENV_EEPROM_IS_ON_I2C
215#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
216#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
217#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
218#define CONFIG_SYS_EEPROM_SIZE 256
219
Igor Grinbergb09bf722014-11-05 14:25:35 +0200220#endif /* __CONFIG_H */