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Phil Edworthy99744b72012-05-15 22:15:51 +00001/*
2 * Copyright (C) 2012 Renesas Electronics Europe Ltd.
3 * Copyright (C) 2012 Phil Edworthy
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
6 *
7 * Based on board/renesas/rsk7264/lowlevel_init.S
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Phil Edworthy99744b72012-05-15 22:15:51 +000010 */
11#include <config.h>
12#include <version.h>
13
14#include <asm/processor.h>
15#include <asm/macro.h>
16
17 .global lowlevel_init
18
19 .text
20 .align 2
21
22lowlevel_init:
23 /* Flush and enable caches (data cache in write-through mode) */
24 write32 CCR1_A ,CCR1_D
25
26 /* Disable WDT */
27 write16 WTCSR_A, WTCSR_D
28 write16 WTCNT_A, WTCNT_D
29
30 /* Disable Register Bank interrupts */
31 write16 IBNR_A, IBNR_D
32
33 /* Set clocks based on 13.225MHz xtal */
34 write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */
35
36 /* Enable all peripherals */
37 write8 STBCR3_A, STBCR3_D
38 write8 STBCR4_A, STBCR4_D
39 write8 STBCR5_A, STBCR5_D
40 write8 STBCR6_A, STBCR6_D
41 write8 STBCR7_A, STBCR7_D
42 write8 STBCR8_A, STBCR8_D
43 write8 STBCR9_A, STBCR9_D
44 write8 STBCR10_A, STBCR10_D
45
46 /* SCIF7 and IIC2 */
47 write16 PJCR3_A, PJCR3_D /* TXD7 */
48 write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */
49
50 /* Configure bus (CS0) */
51 write16 PFCR3_A, PFCR3_D /* A24 */
52 write16 PFCR2_A, PFCR2_D /* A23 and CS1# */
53 write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */
54 write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
55 write32 CS0WCR_A, CS0WCR_D
56 write32 CS0BCR_A, CS0BCR_D
57
58 /* Configure SDRAM (CS3) */
59 write16 PCCR2_A, PCCR2_D /* CS3# */
60 write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */
61 write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */
62 write32 CS3BCR_A, CS3BCR_D
63 write32 CS3WCR_A, CS3WCR_D
64 write32 SDCR_A, SDCR_D
65 write32 RTCOR_A, RTCOR_D
66 write32 RTCSR_A, RTCSR_D
67
68 /* Configure ethernet (CS1) */
69 write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */
70 write16 PHCR0_A, PHCR0_D
71 write16 PFCR2_A, PFCR2_D /* CS1# */
72 write32 CS1BCR_A, CS1BCR_D /* Big endian */
73 write32 CS1WCR_A, CS1WCR_D /* 1 cycle */
74 write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */
75 write16 PJIOR1_A, PJIOR1_D
76
77 /* wait 200us */
78 mov.l REPEAT_D, r3
79 mov #0, r2
80repeat0:
81 add #1, r2
82 cmp/hs r3, r2
83 bf repeat0
84 nop
85
86 mov.l SDRAM_MODE, r1
87 mov #0, r0
88 mov.l r0, @r1
89
90 nop
91 rts
92
93 .align 4
94
95CCR1_A: .long CCR1
96CCR1_D: .long 0x0000090B
97
98STBCR3_A: .long 0xFFFE0408
99STBCR4_A: .long 0xFFFE040C
100STBCR5_A: .long 0xFFFE0410
101STBCR6_A: .long 0xFFFE0414
102STBCR7_A: .long 0xFFFE0418
103STBCR8_A: .long 0xFFFE041C
104STBCR9_A: .long 0xFFFE0440
105STBCR10_A: .long 0xFFFE0444
106STBCR3_D: .long 0x0000001A
107STBCR4_D: .long 0x00000000
108STBCR5_D: .long 0x00000000
109STBCR6_D: .long 0x00000000
110STBCR7_D: .long 0x00000012
111STBCR8_D: .long 0x00000009
112STBCR9_D: .long 0x00000000
113STBCR10_D: .long 0x00000010
114
115WTCSR_A: .long 0xFFFE0000
116WTCNT_A: .long 0xFFFE0002
117WTCSR_D: .word 0xA518
118WTCNT_D: .word 0x5A00
119
120IBNR_A: .long 0xFFFE080E
121IBNR_D: .word 0x0000
122.align 2
123FRQCR_A: .long 0xFFFE0010
124FRQCR_D: .word 0x0015
125.align 2
126
127PJCR3_A: .long 0xFFFE3908
128PJCR3_D: .word 0x5000
129.align 2
130PECR1_A: .long 0xFFFE388C
131PECR1_D: .word 0x2011
132.align 2
133
134PFCR3_A: .long 0xFFFE38A8
135PFCR2_A: .long 0xFFFE38AA
136PBCR5_A: .long 0xFFFE3824
137PFCR3_D: .word 0x0010
138PFCR2_D: .word 0x0101
139PBCR5_D: .word 0x0111
140.align 2
141CS0WCR_A: .long 0xFFFC0028
142CS0WCR_D: .long 0x00000341
143CS0BCR_A: .long 0xFFFC0004
144CS0BCR_D: .long 0x00000400
145
146PCCR2_A: .long 0xFFFE384A
147PCCR1_A: .long 0xFFFE384C
148PCCR0_A: .long 0xFFFE384E
149PCCR2_D: .word 0x0001
150PCCR1_D: .word 0x1111
151PCCR0_D: .word 0x1111
152.align 2
153CS3BCR_A: .long 0xFFFC0010
154CS3BCR_D: .long 0x00004400
155CS3WCR_A: .long 0xFFFC0034
156CS3WCR_D: .long 0x00004912
157SDCR_A: .long 0xFFFC004C
158SDCR_D: .long 0x00000811
159RTCOR_A: .long 0xFFFC0058
160RTCOR_D: .long 0xA55A0035
161RTCSR_A: .long 0xFFFC0050
162RTCSR_D: .long 0xA55A0010
163.align 2
164SDRAM_MODE: .long 0xFFFC5460
165REPEAT_D: .long 0x000033F1
166
167PHCR1_A: .long 0xFFFE38EC
168PHCR0_A: .long 0xFFFE38EE
169PHCR1_D: .word 0x2222
170PHCR0_D: .word 0x2222
171.align 2
172CS1BCR_A: .long 0xFFFC0008
173CS1BCR_D: .long 0x00000400
174CS1WCR_A: .long 0xFFFC002C
175CS1WCR_D: .long 0x00000080
176PJDR1_A: .long 0xFFFE3914
177PJDR1_D: .word 0x0000
178.align 2
179PJIOR1_A: .long 0xFFFE3910
180PJIOR1_D: .word 0x8000
181.align 2