Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / cd18f1e6e6144bd72110b07144e77f9e84b2e7c8 / . / arch / arm / dts / imx6qdl-gw51xx.dtsi
blob: 7e28463084a69d16531c8bf05701f95655f90a95 [file] [log] [blame]
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 nand = &gpmi;
16 usb0 = &usbh1;
17 usb1 = &usbotg;
18 };
19
20 chosen {
21 bootargs = "console=ttymxc1,115200";
22 };
23
24 gpio-keys {
25 compatible = "gpio-keys";
26
27 user-pb {
28 label = "user_pb";
29 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
30 linux,code = <BTN_0>;
31 };
32
33 user-pb1x {
34 label = "user_pb1x";
35 linux,code = <BTN_1>;
36 interrupt-parent = <&gsc>;
37 interrupts = <0>;
38 };
39
40 key-erased {
41 label = "key-erased";
42 linux,code = <BTN_2>;
43 interrupt-parent = <&gsc>;
44 interrupts = <1>;
45 };
46
47 eeprom-wp {
48 label = "eeprom_wp";
49 linux,code = <BTN_3>;
50 interrupt-parent = <&gsc>;
51 interrupts = <2>;
52 };
53
54 tamper {
55 label = "tamper";
56 linux,code = <BTN_4>;
57 interrupt-parent = <&gsc>;
58 interrupts = <5>;
59 };
60
61 switch-hold {
62 label = "switch_hold";
63 linux,code = <BTN_5>;
64 interrupt-parent = <&gsc>;
65 interrupts = <7>;
66 };
67 };
68
69 leds {
70 compatible = "gpio-leds";
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_gpio_leds>;
73
74 led0: user1 {
75 label = "user1";
76 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
77 default-state = "on";
78 linux,default-trigger = "heartbeat";
79 };
80
81 led1: user2 {
82 label = "user2";
83 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
84 default-state = "off";
85 };
86 };
87
88 memory@10000000 {
89 device_type = "memory";
90 reg = <0x10000000 0x20000000>;
91 };
92
93 pps {
94 compatible = "pps-gpio";
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_pps>;
97 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
98 status = "okay";
99 };
100
101 reg_3p3v: regulator-3p3v {
102 compatible = "regulator-fixed";
103 regulator-name = "3P3V";
104 regulator-min-microvolt = <3300000>;
105 regulator-max-microvolt = <3300000>;
106 regulator-always-on;
107 };
108
109 reg_5p0v: regulator-5p0v {
110 compatible = "regulator-fixed";
111 regulator-name = "5P0V";
112 regulator-min-microvolt = <5000000>;
113 regulator-max-microvolt = <5000000>;
114 regulator-always-on;
115 };
116
117 reg_usb_otg_vbus: regulator-usb-otg-vbus {
118 compatible = "regulator-fixed";
119 regulator-name = "usb_otg_vbus";
120 regulator-min-microvolt = <5000000>;
121 regulator-max-microvolt = <5000000>;
122 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
123 enable-active-high;
124 };
125};
126
127&fec {
128 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_enet>;
130 phy-mode = "rgmii-id";
131 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
Tim Harveycd18f1e2021-05-03 11:21:27 -0700[diff] [blame^]132 phy-reset-duration = <10>;
133 phy-reset-post-delay = <100>;
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]134 status = "okay";
135};
136
137&gpmi {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_gpmi_nand>;
140 status = "okay";
141};
142
143&hdmi {
144 ddc-i2c-bus = <&i2c3>;
145 status = "okay";
146};
147
148&i2c1 {
149 clock-frequency = <100000>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_i2c1>;
152 status = "okay";
153
154 gsc: gsc@20 {
155 compatible = "gw,gsc";
156 reg = <0x20>;
157 interrupt-parent = <&gpio1>;
158 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
159 interrupt-controller;
160 #interrupt-cells = <1>;
161 #size-cells = <0>;
162
163 adc {
164 compatible = "gw,gsc-adc";
165 #address-cells = <1>;
166 #size-cells = <0>;
167
168 channel@0 {
169 gw,mode = <0>;
170 reg = <0x00>;
171 label = "temp";
172 };
173
174 channel@2 {
175 gw,mode = <1>;
176 reg = <0x02>;
177 label = "vdd_vin";
178 };
179
180 channel@5 {
181 gw,mode = <1>;
182 reg = <0x05>;
183 label = "vdd_3p3";
184 };
185
186 channel@8 {
187 gw,mode = <1>;
188 reg = <0x08>;
189 label = "vdd_bat";
190 };
191
192 channel@b {
193 gw,mode = <1>;
194 reg = <0x0b>;
195 label = "vdd_5p0";
196 };
197
198 channel@e {
199 gw,mode = <1>;
200 reg = <0xe>;
201 label = "vdd_arm";
202 };
203
204 channel@11 {
205 gw,mode = <1>;
206 reg = <0x11>;
207 label = "vdd_soc";
208 };
209
210 channel@14 {
211 gw,mode = <1>;
212 reg = <0x14>;
213 label = "vdd_3p0";
214 };
215
216 channel@17 {
217 gw,mode = <1>;
218 reg = <0x17>;
219 label = "vdd_1p5";
220 };
221
222 channel@1d {
223 gw,mode = <1>;
224 reg = <0x1d>;
225 label = "vdd_1p8";
226 };
227
228 channel@20 {
229 gw,mode = <1>;
230 reg = <0x20>;
231 label = "vdd_an1";
232 };
233
234 channel@23 {
235 gw,mode = <1>;
236 reg = <0x23>;
237 label = "vdd_2p5";
238 };
239 };
240 };
241
242 gsc_gpio: gpio@23 {
243 compatible = "nxp,pca9555";
244 reg = <0x23>;
245 gpio-controller;
246 #gpio-cells = <2>;
247 interrupt-parent = <&gsc>;
248 interrupts = <4>;
249 };
250
251 eeprom1: eeprom@50 {
252 compatible = "atmel,24c02";
253 reg = <0x50>;
254 pagesize = <16>;
255 };
256
257 eeprom2: eeprom@51 {
258 compatible = "atmel,24c02";
259 reg = <0x51>;
260 pagesize = <16>;
261 };
262
263 eeprom3: eeprom@52 {
264 compatible = "atmel,24c02";
265 reg = <0x52>;
266 pagesize = <16>;
267 };
268
269 eeprom4: eeprom@53 {
270 compatible = "atmel,24c02";
271 reg = <0x53>;
272 pagesize = <16>;
273 };
274
275 rtc: ds1672@68 {
276 compatible = "dallas,ds1672";
277 reg = <0x68>;
278 };
279};
280
281&i2c2 {
282 clock-frequency = <100000>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_i2c2>;
285 status = "okay";
286
287 ltc3676: pmic@3c {
288 compatible = "lltc,ltc3676";
289 reg = <0x3c>;
290 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_pmic>;
292 interrupt-parent = <&gpio1>;
293 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
294
295 regulators {
296 /* VDD_SOC (1+R1/R2 = 1.635) */
297 reg_vdd_soc: sw1 {
298 regulator-name = "vddsoc";
299 regulator-min-microvolt = <674400>;
300 regulator-max-microvolt = <1308000>;
301 lltc,fb-voltage-divider = <127000 200000>;
302 regulator-ramp-delay = <7000>;
303 regulator-boot-on;
304 regulator-always-on;
305 };
306
307 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
308 reg_1p8v: sw2 {
309 regulator-name = "vdd1p8";
310 regulator-min-microvolt = <1033310>;
311 regulator-max-microvolt = <2004000>;
312 lltc,fb-voltage-divider = <301000 200000>;
313 regulator-ramp-delay = <7000>;
314 regulator-boot-on;
315 regulator-always-on;
316 };
317
318 /* VDD_ARM (1+R1/R2 = 1.635) */
319 reg_vdd_arm: sw3 {
320 regulator-name = "vddarm";
321 regulator-min-microvolt = <674400>;
322 regulator-max-microvolt = <1308000>;
323 lltc,fb-voltage-divider = <127000 200000>;
324 regulator-ramp-delay = <7000>;
325 regulator-boot-on;
326 regulator-always-on;
327 };
328
329 /* VDD_DDR (1+R1/R2 = 2.105) */
330 reg_vdd_ddr: sw4 {
331 regulator-name = "vddddr";
332 regulator-min-microvolt = <868310>;
333 regulator-max-microvolt = <1684000>;
334 lltc,fb-voltage-divider = <221000 200000>;
335 regulator-ramp-delay = <7000>;
336 regulator-boot-on;
337 regulator-always-on;
338 };
339
340 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
341 reg_2p5v: ldo2 {
342 regulator-name = "vdd2p5";
343 regulator-min-microvolt = <2490375>;
344 regulator-max-microvolt = <2490375>;
345 lltc,fb-voltage-divider = <487000 200000>;
346 regulator-boot-on;
347 regulator-always-on;
348 };
349
350 /* VDD_HIGH (1+R1/R2 = 4.17) */
351 reg_3p0v: ldo4 {
352 regulator-name = "vdd3p0";
353 regulator-min-microvolt = <3023250>;
354 regulator-max-microvolt = <3023250>;
355 lltc,fb-voltage-divider = <634000 200000>;
356 regulator-boot-on;
357 regulator-always-on;
358 };
359 };
360 };
361};
362
363&i2c3 {
364 clock-frequency = <100000>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_i2c3>;
367 status = "okay";
368
369 adv7180: camera@20 {
370 compatible = "adi,adv7180";
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_adv7180>;
373 reg = <0x20>;
374 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
375 interrupt-parent = <&gpio5>;
376 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
377
378 port {
379 adv7180_to_ipu1_csi0_mux: endpoint {
380 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
381 bus-width = <8>;
382 };
383 };
384 };
385};
386
387&ipu1_csi0_from_ipu1_csi0_mux {
388 bus-width = <8>;
389};
390
391&ipu1_csi0_mux_from_parallel_sensor {
392 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
393 bus-width = <8>;
394};
395
396&ipu1_csi0 {
397 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_ipu1_csi0>;
399};
400
401&pcie {
402 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_pcie>;
404 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
405 status = "okay";
406};
407
408&pwm2 {
409 pinctrl-names = "default";
410 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
411 status = "disabled";
412};
413
414&pwm3 {
415 pinctrl-names = "default";
416 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
417 status = "disabled";
418};
419
420&pwm4 {
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
423 status = "disabled";
424};
425
426&uart1 {
427 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_uart1>;
429 status = "okay";
430};
431
432&uart2 {
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_uart2>;
435 status = "okay";
436};
437
438&uart3 {
439 pinctrl-names = "default";
440 pinctrl-0 = <&pinctrl_uart3>;
441 status = "okay";
442};
443
444&uart5 {
445 pinctrl-names = "default";
446 pinctrl-0 = <&pinctrl_uart5>;
447 status = "okay";
448};
449
450&usbotg {
451 vbus-supply = <&reg_usb_otg_vbus>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pinctrl_usbotg>;
454 disable-over-current;
Tim Harvey13acc632021-03-01 14:33:31 -0800[diff] [blame]455 dr_mode = "otg";
Tim Harveyacb9a132021-03-01 14:33:30 -0800[diff] [blame]456 status = "okay";
457};
458
459&usbh1 {
460 status = "okay";
461};
462
463&wdog1 {
464 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_wdog>;
466 fsl,ext-reset-output;
467};
468
469&iomuxc {
470 pinctrl_adv7180: adv7180grp {
471 fsl,pins = <
472 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0
473 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0
474 >;
475 };
476
477 pinctrl_enet: enetgrp {
478 fsl,pins = <
479 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
480 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
481 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
482 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
483 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
484 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
485 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
486 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
487 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
488 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
489 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
490 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
491 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
492 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
493 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
494 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
495 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
496 >;
497 };
498
499 pinctrl_gpio_leds: gpioledsgrp {
500 fsl,pins = <
501 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
502 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
503 >;
504 };
505
506 pinctrl_gpmi_nand: gpminandgrp {
507 fsl,pins = <
508 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
509 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
510 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
511 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
512 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
513 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
514 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
515 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
516 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
517 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
518 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
519 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
520 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
521 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
522 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
523 >;
524 };
525
526 pinctrl_i2c1: i2c1grp {
527 fsl,pins = <
528 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
529 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
530 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 /* GSC_IRQ# */
531 >;
532 };
533
534 pinctrl_i2c2: i2c2grp {
535 fsl,pins = <
536 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
537 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
538 >;
539 };
540
541 pinctrl_i2c3: i2c3grp {
542 fsl,pins = <
543 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
544 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
545 >;
546 };
547
548 pinctrl_ipu1_csi0: ipu1csi0grp {
549 fsl,pins = <
550 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
551 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
552 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
553 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
554 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
555 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
556 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
557 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
558 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
559 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
560 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
561 >;
562 };
563
564 pinctrl_pcie: pciegrp {
565 fsl,pins = <
566 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
567 >;
568 };
569
570 pinctrl_pmic: pmicgrp {
571 fsl,pins = <
572 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
573 >;
574 };
575
576 pinctrl_pps: ppsgrp {
577 fsl,pins = <
578 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
579 >;
580 };
581
582 pinctrl_pwm2: pwm2grp {
583 fsl,pins = <
584 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
585 >;
586 };
587
588 pinctrl_pwm3: pwm3grp {
589 fsl,pins = <
590 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
591 >;
592 };
593
594 pinctrl_pwm4: pwm4grp {
595 fsl,pins = <
596 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
597 >;
598 };
599
600 pinctrl_uart1: uart1grp {
601 fsl,pins = <
602 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
603 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
604 >;
605 };
606
607 pinctrl_uart2: uart2grp {
608 fsl,pins = <
609 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
610 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
611 >;
612 };
613
614 pinctrl_uart3: uart3grp {
615 fsl,pins = <
616 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
617 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
618 >;
619 };
620
621 pinctrl_uart5: uart5grp {
622 fsl,pins = <
623 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
624 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
625 >;
626 };
627
628 pinctrl_usbotg: usbotggrp {
629 fsl,pins = <
630 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
631 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
632 >;
633 };
634
635 pinctrl_wdog: wdoggrp {
636 fsl,pins = <
637 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
638 >;
639 };
640};