blob: 6c743e3ccc59c47a0606f93fad1af1c5058be225 [file] [log] [blame]
Chunhe Lan0b2e13d2014-04-14 18:42:06 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T4240 RDB board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080013#define CONFIG_FSL_SATA_V2
14#define CONFIG_PCIE4
15
16#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
17
18#ifdef CONFIG_RAMBOOT_PBL
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080019#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
Chunhe Lan373762c2015-03-20 17:08:54 +080020#ifndef CONFIG_SDCARD
21#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
22#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
23#else
Chunhe Lan373762c2015-03-20 17:08:54 +080024#define CONFIG_SPL_FLUSH_IMAGE
25#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Chunhe Lan373762c2015-03-20 17:08:54 +080026#define CONFIG_FSL_LAW /* Use common FSL init code */
27#define CONFIG_SYS_TEXT_BASE 0x00201000
28#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
29#define CONFIG_SPL_PAD_TO 0x40000
30#define CONFIG_SPL_MAX_SIZE 0x28000
31#define RESET_VECTOR_OFFSET 0x27FFC
32#define BOOT_PAGE_OFFSET 0x27000
33
34#ifdef CONFIG_SDCARD
35#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Chunhe Lan373762c2015-03-20 17:08:54 +080036#define CONFIG_SPL_MMC_MINIMAL
37#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
38#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
39#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
40#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
41#ifndef CONFIG_SPL_BUILD
42#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080043#endif
Chunhe Lan373762c2015-03-20 17:08:54 +080044#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
Zhao Qiangec90ac72016-09-08 12:55:32 +080045#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg
Chunhe Lan373762c2015-03-20 17:08:54 +080046#define CONFIG_SPL_MMC_BOOT
47#endif
48
49#ifdef CONFIG_SPL_BUILD
50#define CONFIG_SPL_SKIP_RELOCATE
51#define CONFIG_SPL_COMMON_INIT_DDR
52#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
53#define CONFIG_SYS_NO_FLASH
54#endif
55
56#endif
57#endif /* CONFIG_RAMBOOT_PBL */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080058
59#define CONFIG_DDR_ECC
60
61#define CONFIG_CMD_REGINFO
62
63/* High Level Configuration Options */
64#define CONFIG_BOOKE
65#define CONFIG_E500 /* BOOKE e500 family */
66#define CONFIG_E500MC /* BOOKE e500mc family */
67#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
68#define CONFIG_MP /* support multiple processors */
69
70#ifndef CONFIG_SYS_TEXT_BASE
71#define CONFIG_SYS_TEXT_BASE 0xeff40000
72#endif
73
74#ifndef CONFIG_RESET_VECTOR_ADDRESS
75#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
76#endif
77
78#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
79#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
80#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053081#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040082#define CONFIG_PCIE1 /* PCIE controller 1 */
83#define CONFIG_PCIE2 /* PCIE controller 2 */
84#define CONFIG_PCIE3 /* PCIE controller 3 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080085#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
86#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
87
88#define CONFIG_FSL_LAW /* Use common FSL init code */
89
90#define CONFIG_ENV_OVERWRITE
91
92/*
93 * These can be toggled for performance analysis, otherwise use default.
94 */
95#define CONFIG_SYS_CACHE_STASHING
96#define CONFIG_BTB /* toggle branch predition */
97#ifdef CONFIG_DDR_ECC
98#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
99#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
100#endif
101
102#define CONFIG_ENABLE_36BIT_PHYS
103
104#define CONFIG_ADDR_MAP
105#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
106
107#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
108#define CONFIG_SYS_MEMTEST_END 0x00400000
109#define CONFIG_SYS_ALT_MEMTEST
110#define CONFIG_PANIC_HANG /* do not reset board on panic */
111
112/*
113 * Config the L3 Cache as L3 SRAM
114 */
Chunhe Lan373762c2015-03-20 17:08:54 +0800115#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
116#define CONFIG_SYS_L3_SIZE (512 << 10)
117#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
118#ifdef CONFIG_RAMBOOT_PBL
119#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
120#endif
121#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
122#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
123#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
124#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800125
126#define CONFIG_SYS_DCSRBAR 0xf0000000
127#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
128
129/*
130 * DDR Setup
131 */
132#define CONFIG_VERY_BIG_RAM
133#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
134#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
135
136/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
137#define CONFIG_DIMM_SLOTS_PER_CTLR 1
138#define CONFIG_CHIP_SELECTS_PER_CTRL 4
139#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
140
141#define CONFIG_DDR_SPD
142#define CONFIG_SYS_FSL_DDR3
143
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800144/*
145 * IFC Definitions
146 */
147#define CONFIG_SYS_FLASH_BASE 0xe0000000
148#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
149
Chunhe Lan373762c2015-03-20 17:08:54 +0800150#ifdef CONFIG_SPL_BUILD
151#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
152#else
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800153#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Chunhe Lan373762c2015-03-20 17:08:54 +0800154#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800155
156#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
157#define CONFIG_MISC_INIT_R
158
159#define CONFIG_HWCONFIG
160
161/* define to use L1 as initial stack */
162#define CONFIG_L1_INIT_RAM
163#define CONFIG_SYS_INIT_RAM_LOCK
164#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
165#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700166#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800167/* The assembler doesn't like typecast */
168#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
169 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
170 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
171#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
172
173#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
174 GENERATED_GBL_DATA_SIZE)
175#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
176
Chunhe Lan373762c2015-03-20 17:08:54 +0800177#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800178#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
179
180/* Serial Port - controlled on board with jumper J8
181 * open - index 2
182 * shorted - index 1
183 */
184#define CONFIG_CONS_INDEX 1
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800185#define CONFIG_SYS_NS16550_SERIAL
186#define CONFIG_SYS_NS16550_REG_SIZE 1
187#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
188
189#define CONFIG_SYS_BAUDRATE_TABLE \
190 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
191
192#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
193#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
194#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
195#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
196
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800197/* I2C */
198#define CONFIG_SYS_I2C
199#define CONFIG_SYS_I2C_FSL
200#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
201#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
202#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
203#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
204
205/*
206 * General PCI
207 * Memory space is mapped 1-1, but I/O space must start from 0.
208 */
209
210/* controller 1, direct to uli, tgtid 3, Base address 20000 */
211#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
212#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
213#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
214#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
215#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
216#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
217#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
218#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
219
220/* controller 2, Slot 2, tgtid 2, Base address 201000 */
221#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
222#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
223#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
224#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
225#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
226#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
227#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
228#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
229
230/* controller 3, Slot 1, tgtid 1, Base address 202000 */
231#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
232#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
233#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
234#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
235#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
236#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
237#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
238#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
239
240/* controller 4, Base address 203000 */
241#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
242#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
243#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
244#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
245#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
246#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
247
248#ifdef CONFIG_PCI
249#define CONFIG_PCI_INDIRECT_BRIDGE
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800250
251#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
252#define CONFIG_DOS_PARTITION
253#endif /* CONFIG_PCI */
254
255/* SATA */
256#ifdef CONFIG_FSL_SATA_V2
257#define CONFIG_LIBATA
258#define CONFIG_FSL_SATA
259
260#define CONFIG_SYS_SATA_MAX_DEVICE 2
261#define CONFIG_SATA1
262#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
263#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
264#define CONFIG_SATA2
265#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
266#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
267
268#define CONFIG_LBA48
269#define CONFIG_CMD_SATA
270#define CONFIG_DOS_PARTITION
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800271#endif
272
273#ifdef CONFIG_FMAN_ENET
274#define CONFIG_MII /* MII PHY management */
275#define CONFIG_ETHPRIME "FM1@DTSEC1"
276#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
277#endif
278
279/*
280 * Environment
281 */
282#define CONFIG_LOADS_ECHO /* echo on for serial download */
283#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
284
285/*
286 * Command line configuration.
287 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800288#define CONFIG_CMD_ERRATA
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800289#define CONFIG_CMD_IRQ
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800290
291#ifdef CONFIG_PCI
292#define CONFIG_CMD_PCI
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800293#endif
294
295/*
296 * Miscellaneous configurable options
297 */
298#define CONFIG_SYS_LONGHELP /* undef to save memory */
299#define CONFIG_CMDLINE_EDITING /* Command-line editing */
300#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
301#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
302#ifdef CONFIG_CMD_KGDB
303#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
304#else
305#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
306#endif
307#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
308#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
309#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
310
311/*
312 * For booting Linux, the board info and command line data
313 * have to be in the first 64 MB of memory, since this is
314 * the maximum mapped by the Linux kernel during initialization.
315 */
316#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
317#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
318
319#ifdef CONFIG_CMD_KGDB
320#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
321#endif
322
323/*
324 * Environment Configuration
325 */
326#define CONFIG_ROOTPATH "/opt/nfsroot"
327#define CONFIG_BOOTFILE "uImage"
328#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
329
330/* default location for tftp and bootm */
331#define CONFIG_LOADADDR 1000000
332
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800333#define CONFIG_BAUDRATE 115200
334
335#define CONFIG_HVBOOT \
336 "setenv bootargs config-addr=0x60000000; " \
337 "bootm 0x01000000 - 0x00f00000"
338
339#ifdef CONFIG_SYS_NO_FLASH
340#ifndef CONFIG_RAMBOOT_PBL
341#define CONFIG_ENV_IS_NOWHERE
342#endif
343#else
344#define CONFIG_FLASH_CFI_DRIVER
345#define CONFIG_SYS_FLASH_CFI
346#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
347#endif
348
349#if defined(CONFIG_SPIFLASH)
350#define CONFIG_SYS_EXTRA_ENV_RELOC
351#define CONFIG_ENV_IS_IN_SPI_FLASH
352#define CONFIG_ENV_SPI_BUS 0
353#define CONFIG_ENV_SPI_CS 0
354#define CONFIG_ENV_SPI_MAX_HZ 10000000
355#define CONFIG_ENV_SPI_MODE 0
356#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
357#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
358#define CONFIG_ENV_SECT_SIZE 0x10000
359#elif defined(CONFIG_SDCARD)
360#define CONFIG_SYS_EXTRA_ENV_RELOC
361#define CONFIG_ENV_IS_IN_MMC
362#define CONFIG_SYS_MMC_ENV_DEV 0
363#define CONFIG_ENV_SIZE 0x2000
Chunhe Lan373762c2015-03-20 17:08:54 +0800364#define CONFIG_ENV_OFFSET (512 * 0x800)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800365#elif defined(CONFIG_NAND)
366#define CONFIG_SYS_EXTRA_ENV_RELOC
367#define CONFIG_ENV_IS_IN_NAND
368#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
369#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
370#elif defined(CONFIG_ENV_IS_NOWHERE)
371#define CONFIG_ENV_SIZE 0x2000
372#else
373#define CONFIG_ENV_IS_IN_FLASH
374#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
375#define CONFIG_ENV_SIZE 0x2000
376#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
377#endif
378
379#define CONFIG_SYS_CLK_FREQ 66666666
380#define CONFIG_DDR_CLK_FREQ 133333333
381
382#ifndef __ASSEMBLY__
383unsigned long get_board_sys_clk(void);
384unsigned long get_board_ddr_clk(void);
385#endif
386
387/*
388 * DDR Setup
389 */
390#define CONFIG_SYS_SPD_BUS_NUM 0
391#define SPD_EEPROM_ADDRESS1 0x52
392#define SPD_EEPROM_ADDRESS2 0x54
393#define SPD_EEPROM_ADDRESS3 0x56
394#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
395#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
396
397/*
398 * IFC Definitions
399 */
400#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
401#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
402 + 0x8000000) | \
403 CSPR_PORT_SIZE_16 | \
404 CSPR_MSEL_NOR | \
405 CSPR_V)
406#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
407#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
408 CSPR_PORT_SIZE_16 | \
409 CSPR_MSEL_NOR | \
410 CSPR_V)
411#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
412/* NOR Flash Timing Params */
413#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
414
415#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
416 FTIM0_NOR_TEADC(0x5) | \
417 FTIM0_NOR_TEAHC(0x5))
418#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
419 FTIM1_NOR_TRAD_NOR(0x1A) |\
420 FTIM1_NOR_TSEQRAD_NOR(0x13))
421#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
422 FTIM2_NOR_TCH(0x4) | \
423 FTIM2_NOR_TWPH(0x0E) | \
424 FTIM2_NOR_TWP(0x1c))
425#define CONFIG_SYS_NOR_FTIM3 0x0
426
427#define CONFIG_SYS_FLASH_QUIET_TEST
428#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
429
430#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
431#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
432#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
433#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
434
435#define CONFIG_SYS_FLASH_EMPTY_INFO
436#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
437 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
438
439/* NAND Flash on IFC */
440#define CONFIG_NAND_FSL_IFC
441#define CONFIG_SYS_NAND_MAX_ECCPOS 256
442#define CONFIG_SYS_NAND_MAX_OOBFREE 2
443#define CONFIG_SYS_NAND_BASE 0xff800000
444#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
445
446#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
447#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
448 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
449 | CSPR_MSEL_NAND /* MSEL = NAND */ \
450 | CSPR_V)
451#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
452
453#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
454 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
455 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
456 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
457 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
458 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
459 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
460
461#define CONFIG_SYS_NAND_ONFI_DETECTION
462
463/* ONFI NAND Flash mode0 Timing Params */
464#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
465 FTIM0_NAND_TWP(0x18) | \
466 FTIM0_NAND_TWCHT(0x07) | \
467 FTIM0_NAND_TWH(0x0a))
468#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
469 FTIM1_NAND_TWBE(0x39) | \
470 FTIM1_NAND_TRR(0x0e) | \
471 FTIM1_NAND_TRP(0x18))
472#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
473 FTIM2_NAND_TREH(0x0a) | \
474 FTIM2_NAND_TWHRE(0x1e))
475#define CONFIG_SYS_NAND_FTIM3 0x0
476
477#define CONFIG_SYS_NAND_DDR_LAW 11
478#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
479#define CONFIG_SYS_MAX_NAND_DEVICE 1
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800480#define CONFIG_CMD_NAND
481
482#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
483
484#if defined(CONFIG_NAND)
485#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
486#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
487#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
488#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
489#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
490#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
491#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
492#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
493#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
494#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
495#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
496#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
497#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
498#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
499#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
500#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
501#else
502#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
503#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
504#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
505#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
506#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
507#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
508#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
509#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
510#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
511#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
512#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
513#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
514#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
515#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
516#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
517#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
518#endif
519#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
520#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
521#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
522#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
523#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
524#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
525#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
526#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
527
Chunhe Lanab06b232014-09-12 14:47:09 +0800528/* CPLD on IFC */
529#define CONFIG_SYS_CPLD_BASE 0xffdf0000
530#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
531#define CONFIG_SYS_CSPR3_EXT (0xf)
532#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
533 | CSPR_PORT_SIZE_8 \
534 | CSPR_MSEL_GPCM \
535 | CSPR_V)
536
537#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
538#define CONFIG_SYS_CSOR3 0x0
539
540/* CPLD Timing parameters for IFC CS3 */
541#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
542 FTIM0_GPCM_TEADC(0x0e) | \
543 FTIM0_GPCM_TEAHC(0x0e))
544#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
545 FTIM1_GPCM_TRAD(0x1f))
546#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Chunhe Lan1b5c2b52014-10-20 16:03:15 +0800547 FTIM2_GPCM_TCH(0x8) | \
Chunhe Lanab06b232014-09-12 14:47:09 +0800548 FTIM2_GPCM_TWP(0x1f))
549#define CONFIG_SYS_CS3_FTIM3 0x0
550
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800551#if defined(CONFIG_RAMBOOT_PBL)
552#define CONFIG_SYS_RAMBOOT
553#endif
554
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800555/* I2C */
556#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
557#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
558#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
559#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
560
561#define I2C_MUX_CH_DEFAULT 0x8
562#define I2C_MUX_CH_VOL_MONITOR 0xa
563#define I2C_MUX_CH_VSC3316_FS 0xc
564#define I2C_MUX_CH_VSC3316_BS 0xd
565
566/* Voltage monitor on channel 2*/
567#define I2C_VOL_MONITOR_ADDR 0x40
568#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
569#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
570#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
571
Ying Zhang2f66a822016-01-22 12:15:13 +0800572#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv"
573#ifndef CONFIG_SPL_BUILD
574#define CONFIG_VID
575#endif
576#define CONFIG_VOL_MONITOR_IR36021_SET
577#define CONFIG_VOL_MONITOR_IR36021_READ
578/* The lowest and highest voltage allowed for T4240RDB */
579#define VDD_MV_MIN 819
580#define VDD_MV_MAX 1212
581
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800582/*
583 * eSPI - Enhanced SPI
584 */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800585#define CONFIG_SF_DEFAULT_SPEED 10000000
586#define CONFIG_SF_DEFAULT_MODE 0
587
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800588/* Qman/Bman */
589#ifndef CONFIG_NOBQFMAN
590#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
591#define CONFIG_SYS_BMAN_NUM_PORTALS 50
592#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
593#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
594#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500595#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
596#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
597#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
598#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
599#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
600 CONFIG_SYS_BMAN_CENA_SIZE)
601#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
602#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800603#define CONFIG_SYS_QMAN_NUM_PORTALS 50
604#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
605#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
606#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500607#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
608#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
609#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
610#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
611#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
612 CONFIG_SYS_QMAN_CENA_SIZE)
613#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
614#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800615
616#define CONFIG_SYS_DPAA_FMAN
617#define CONFIG_SYS_DPAA_PME
618#define CONFIG_SYS_PMAN
619#define CONFIG_SYS_DPAA_DCE
620#define CONFIG_SYS_DPAA_RMAN
621#define CONFIG_SYS_INTERLAKEN
622
623/* Default address of microcode for the Linux Fman driver */
624#if defined(CONFIG_SPIFLASH)
625/*
626 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
627 * env, so we got 0x110000.
628 */
629#define CONFIG_SYS_QE_FW_IN_SPIFLASH
630#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
631#elif defined(CONFIG_SDCARD)
632/*
633 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Chunhe Lan373762c2015-03-20 17:08:54 +0800634 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
635 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800636 */
637#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Chunhe Lan373762c2015-03-20 17:08:54 +0800638#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800639#elif defined(CONFIG_NAND)
640#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
641#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
642#else
643#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
644#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
645#endif
646#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
647#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
648#endif /* CONFIG_NOBQFMAN */
649
650#ifdef CONFIG_SYS_DPAA_FMAN
651#define CONFIG_FMAN_ENET
652#define CONFIG_PHYLIB_10G
653#define CONFIG_PHY_VITESSE
654#define CONFIG_PHY_CORTINA
Chunhe Lana8efe792015-03-24 15:10:41 +0800655#define CONFIG_SYS_CORTINA_FW_IN_NOR
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800656#define CONFIG_CORTINA_FW_ADDR 0xefe00000
657#define CONFIG_CORTINA_FW_LENGTH 0x40000
658#define CONFIG_PHY_TERANETICS
659#define SGMII_PHY_ADDR1 0x0
660#define SGMII_PHY_ADDR2 0x1
661#define SGMII_PHY_ADDR3 0x2
662#define SGMII_PHY_ADDR4 0x3
663#define SGMII_PHY_ADDR5 0x4
664#define SGMII_PHY_ADDR6 0x5
665#define SGMII_PHY_ADDR7 0x6
666#define SGMII_PHY_ADDR8 0x7
667#define FM1_10GEC1_PHY_ADDR 0x10
668#define FM1_10GEC2_PHY_ADDR 0x11
669#define FM2_10GEC1_PHY_ADDR 0x12
670#define FM2_10GEC2_PHY_ADDR 0x13
671#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
672#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
673#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
674#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
675#endif
676
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800677/* SATA */
678#ifdef CONFIG_FSL_SATA_V2
679#define CONFIG_LIBATA
680#define CONFIG_FSL_SATA
681
682#define CONFIG_SYS_SATA_MAX_DEVICE 2
683#define CONFIG_SATA1
684#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
685#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
686#define CONFIG_SATA2
687#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
688#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
689
690#define CONFIG_LBA48
691#define CONFIG_CMD_SATA
692#define CONFIG_DOS_PARTITION
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800693#endif
694
695#ifdef CONFIG_FMAN_ENET
696#define CONFIG_MII /* MII PHY management */
697#define CONFIG_ETHPRIME "FM1@DTSEC1"
698#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
699#endif
700
701/*
702* USB
703*/
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800704#define CONFIG_USB_EHCI
705#define CONFIG_USB_EHCI_FSL
706#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800707#define CONFIG_HAS_FSL_DR_USB
708
709#define CONFIG_MMC
710
711#ifdef CONFIG_MMC
712#define CONFIG_FSL_ESDHC
713#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
714#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800715#define CONFIG_GENERIC_MMC
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800716#define CONFIG_DOS_PARTITION
Xiaobo Xie929dfdc2014-11-18 09:12:24 +0800717#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800718#endif
719
Ruchika Gupta737537e2014-10-15 11:35:31 +0530720/* Hash command with SHA acceleration supported in hardware */
721#ifdef CONFIG_FSL_CAAM
722#define CONFIG_CMD_HASH
723#define CONFIG_SHA_HW_ACCEL
724#endif
725
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800726
727#define __USB_PHY_TYPE utmi
728
729/*
730 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
731 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
732 * interleaving. It can be cacheline, page, bank, superbank.
733 * See doc/README.fsl-ddr for details.
734 */
York Sun26bc57d2016-11-21 13:35:41 -0800735#ifdef CONFIG_ARCH_T4240
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800736#define CTRL_INTLV_PREFERED 3way_4KB
Chunhe Lan1a344452014-05-07 10:56:18 +0800737#else
738#define CTRL_INTLV_PREFERED cacheline
739#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800740
741#define CONFIG_EXTRA_ENV_SETTINGS \
742 "hwconfig=fsl_ddr:" \
743 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
744 "bank_intlv=auto;" \
745 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
746 "netdev=eth0\0" \
747 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
748 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
749 "tftpflash=tftpboot $loadaddr $uboot && " \
750 "protect off $ubootaddr +$filesize && " \
751 "erase $ubootaddr +$filesize && " \
752 "cp.b $loadaddr $ubootaddr $filesize && " \
753 "protect on $ubootaddr +$filesize && " \
754 "cmp.b $loadaddr $ubootaddr $filesize\0" \
755 "consoledev=ttyS0\0" \
756 "ramdiskaddr=2000000\0" \
757 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500758 "fdtaddr=1e00000\0" \
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800759 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
760 "bdev=sda3\0"
761
762#define CONFIG_HVBOOT \
763 "setenv bootargs config-addr=0x60000000; " \
764 "bootm 0x01000000 - 0x00f00000"
765
766#define CONFIG_LINUX \
767 "setenv bootargs root=/dev/ram rw " \
768 "console=$consoledev,$baudrate $othbootargs;" \
769 "setenv ramdiskaddr 0x02000000;" \
770 "setenv fdtaddr 0x00c00000;" \
771 "setenv loadaddr 0x1000000;" \
772 "bootm $loadaddr $ramdiskaddr $fdtaddr"
773
774#define CONFIG_HDBOOT \
775 "setenv bootargs root=/dev/$bdev rw " \
776 "console=$consoledev,$baudrate $othbootargs;" \
777 "tftp $loadaddr $bootfile;" \
778 "tftp $fdtaddr $fdtfile;" \
779 "bootm $loadaddr - $fdtaddr"
780
781#define CONFIG_NFSBOOTCOMMAND \
782 "setenv bootargs root=/dev/nfs rw " \
783 "nfsroot=$serverip:$rootpath " \
784 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
785 "console=$consoledev,$baudrate $othbootargs;" \
786 "tftp $loadaddr $bootfile;" \
787 "tftp $fdtaddr $fdtfile;" \
788 "bootm $loadaddr - $fdtaddr"
789
790#define CONFIG_RAMBOOTCOMMAND \
791 "setenv bootargs root=/dev/ram rw " \
792 "console=$consoledev,$baudrate $othbootargs;" \
793 "tftp $ramdiskaddr $ramdiskfile;" \
794 "tftp $loadaddr $bootfile;" \
795 "tftp $fdtaddr $fdtfile;" \
796 "bootm $loadaddr $ramdiskaddr $fdtaddr"
797
798#define CONFIG_BOOTCOMMAND CONFIG_LINUX
799
800#include <asm/fsl_secure_boot.h>
801
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800802#endif /* __CONFIG_H */