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Dirk Eibacha605ea72010-10-21 10:50:05 +02001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibacha605ea72010-10-21 10:50:05 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibacha605ea72010-10-21 10:50:05 +020012#define CONFIG_IOCON 1 /* on a IoCon board */
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME iocon
Dirk Eibacha605ea72010-10-21 10:50:05 +020020#include "amcc-common.h"
21
Tom Rini57e5eca2016-01-19 13:01:59 -050022/* Reclaim some space. */
23#undef CONFIG_SYS_LONGHELP
24
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000025#define CONFIG_BOARD_EARLY_INIT_F
26#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibacha605ea72010-10-21 10:50:05 +020027#define CONFIG_LAST_STAGE_INIT
28
29#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
30
31/*
32 * Configure PLL
33 */
34#define PLLMR0_DEFAULT PLLMR0_266_133_66
35#define PLLMR1_DEFAULT PLLMR1_266_133_66
36
37/* new uImage format support */
Dirk Eibach9a4f4792014-07-03 09:28:26 +020038#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibacha605ea72010-10-21 10:50:05 +020039
40#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
41
42/*
43 * Default environment variables
44 */
45#define CONFIG_EXTRA_ENV_SETTINGS \
46 CONFIG_AMCC_DEF_ENV \
47 CONFIG_AMCC_DEF_ENV_POWERPC \
48 CONFIG_AMCC_DEF_ENV_NOR_UPD \
49 "kernel_addr=fc000000\0" \
50 "fdt_addr=fc1e0000\0" \
51 "ramdisk_addr=fc200000\0" \
52 ""
53
54#define CONFIG_PHY_ADDR 4 /* PHY address */
55#define CONFIG_HAS_ETH0
56#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
57
58/*
59 * Commands additional to the ones defined in amcc-common.h
60 */
Michal Simek7d2357c2014-06-17 00:36:14 +020061#define CONFIG_CMD_FPGAD
Dirk Eibacha605ea72010-10-21 10:50:05 +020062#undef CONFIG_CMD_EEPROM
Dirk Eibach4fb9b412014-07-03 09:28:25 +020063#undef CONFIG_CMD_IRQ
Dirk Eibacha605ea72010-10-21 10:50:05 +020064
65/*
66 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
67 */
68#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
69
70/* SDRAM timings used in datasheet */
71#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
72#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
73#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
74#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
75#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
76
77/*
78 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
79 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
80 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
81 * The Linux BASE_BAUD define should match this configuration.
82 * baseBaud = cpuClock/(uartDivisor*16)
83 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
84 * set Linux BASE_BAUD to 403200.
85 */
86#define CONFIG_CONS_INDEX 1 /* Use UART0 */
87#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
88#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
89#define CONFIG_SYS_BASE_BAUD 691200
90
91/*
92 * I2C stuff
93 */
Heiko Schocherea818db2013-01-29 08:53:15 +010094#define CONFIG_SYS_I2C
Dirk Eibach880540d2013-04-25 02:40:01 +000095#define CONFIG_SYS_I2C_PPC4XX
96#define CONFIG_SYS_I2C_PPC4XX_CH0
97#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
98#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Dirk Eibachb46226b2014-07-03 09:28:18 +020099#define CONFIG_SYS_I2C_IHS
Dirk Eibacha605ea72010-10-21 10:50:05 +0200100
Dirk Eibache50e8962013-07-25 19:28:13 +0200101#define CONFIG_SYS_I2C_SPEED 400000
Dirk Eibachb46226b2014-07-03 09:28:18 +0200102#define CONFIG_SYS_SPD_BUS_NUM 4
Dirk Eibache50e8962013-07-25 19:28:13 +0200103
104#define CONFIG_PCA953X /* NXP PCA9554 */
105#define CONFIG_PCA9698 /* NXP PCA9698 */
106
Dirk Eibachb46226b2014-07-03 09:28:18 +0200107#define CONFIG_SYS_I2C_IHS_CH0
108#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
109#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
110#define CONFIG_SYS_I2C_IHS_CH1
111#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
112#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
113#define CONFIG_SYS_I2C_IHS_CH2
114#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
115#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
116#define CONFIG_SYS_I2C_IHS_CH3
117#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
118#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
119
Dirk Eibacha605ea72010-10-21 10:50:05 +0200120/*
121 * Software (bit-bang) I2C driver configuration
122 */
Dirk Eibache50e8962013-07-25 19:28:13 +0200123#define CONFIG_SYS_I2C_SOFT
124#define CONFIG_SYS_I2C_SOFT_SPEED 50000
125#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
126#define I2C_SOFT_DECLARATIONS2
127#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
128#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
129#define I2C_SOFT_DECLARATIONS3
130#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
131#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
132#define I2C_SOFT_DECLARATIONS4
133#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
134#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
135
Dirk Eibachb46226b2014-07-03 09:28:18 +0200136#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
137#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
138#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
Dirk Eibacha605ea72010-10-21 10:50:05 +0200139
140#ifndef __ASSEMBLY__
Dirk Eibache50e8962013-07-25 19:28:13 +0200141void fpga_gpio_set(unsigned int bus, int pin);
142void fpga_gpio_clear(unsigned int bus, int pin);
143int fpga_gpio_get(unsigned int bus, int pin);
Dirk Eibacha605ea72010-10-21 10:50:05 +0200144#endif
145
146#define I2C_ACTIVE { }
147#define I2C_TRISTATE { }
Dirk Eibache50e8962013-07-25 19:28:13 +0200148#define I2C_READ \
149 (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
150#define I2C_SDA(bit) \
151 do { \
152 if (bit) \
153 fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
154 else \
155 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
156 } while (0)
157#define I2C_SCL(bit) \
158 do { \
159 if (bit) \
160 fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
161 else \
162 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
163 } while (0)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200164#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
165
166/*
167 * FLASH organization
168 */
169#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
170#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
171
172#define CONFIG_SYS_FLASH_BASE 0xFC000000
173#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
174
175#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
176#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
177
178#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
179#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
180
181#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibacha605ea72010-10-21 10:50:05 +0200182
183#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
184#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
185
186#ifdef CONFIG_ENV_IS_IN_FLASH
187#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
188#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
189#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
190
191/* Address and size of Redundant Environment Sector */
192#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
193#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
194#endif
195
196/*
197 * PPC405 GPIO Configuration
198 */
199#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
200{ \
201/* GPIO Core 0 */ \
202{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
203{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
204{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
205{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
206{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
207{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
208{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
209{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
210{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
211{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
212{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
213{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
214{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
215{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
216{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
217{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
218{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
219{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
220{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
221{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
222{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
223{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
224{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
225{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
226{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
227{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
228{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
229{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
230{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
231{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
232{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
233{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
234} \
235}
236
237/*
238 * Definitions for initial stack pointer and data area (in data cache)
239 */
240/* use on chip memory (OCM) for temperary stack until sdram is tested */
241#define CONFIG_SYS_TEMP_STACK_OCM 1
242
243/* On Chip Memory location */
244#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
245#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
246#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
York Sunb39d1212016-04-06 13:22:10 -0700247#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
Dirk Eibacha605ea72010-10-21 10:50:05 +0200248
Dirk Eibacha605ea72010-10-21 10:50:05 +0200249#define CONFIG_SYS_GBL_DATA_OFFSET \
York Sunb39d1212016-04-06 13:22:10 -0700250 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200251#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
252
253/*
254 * External Bus Controller (EBC) Setup
255 */
256
257/* Memory Bank 0 (NOR-FLASH) initialization */
258#define CONFIG_SYS_EBC_PB0AP 0xa382a880
259#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
260
261/* Memory Bank 1 (NVRAM) initializatio */
262#define CONFIG_SYS_EBC_PB1AP 0x92015480
263#define CONFIG_SYS_EBC_PB1CR 0xFB858000
264
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100265/* Memory Bank 2 (FPGA0) initialization */
266#define CONFIG_SYS_FPGA0_BASE 0x7f100000
Dirk Eibacha605ea72010-10-21 10:50:05 +0200267#define CONFIG_SYS_EBC_PB2AP 0x02825080
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100268#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200269
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100270#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
271#define CONFIG_SYS_FPGA_DONE(k) 0x0010
272
273#define CONFIG_SYS_FPGA_COUNT 1
Dirk Eibacha605ea72010-10-21 10:50:05 +0200274
Dirk Eibache50e8962013-07-25 19:28:13 +0200275#define CONFIG_SYS_MCLINK_MAX 3
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200276
Dirk Eibache50e8962013-07-25 19:28:13 +0200277#define CONFIG_SYS_FPGA_PTR \
278 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200279
Dirk Eibacha605ea72010-10-21 10:50:05 +0200280/* Memory Bank 3 (Latches) initialization */
281#define CONFIG_SYS_LATCH_BASE 0x7f200000
282#define CONFIG_SYS_EBC_PB3AP 0x02025080
283#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
284
285#define CONFIG_SYS_LATCH0_RESET 0xffef
286#define CONFIG_SYS_LATCH0_BOOT 0xffff
287#define CONFIG_SYS_LATCH1_RESET 0xffff
288#define CONFIG_SYS_LATCH1_BOOT 0xffff
289
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100290/*
291 * OSD Setup
292 */
293#define CONFIG_SYS_MPC92469AC
Dirk Eibache50e8962013-07-25 19:28:13 +0200294#define CONFIG_SYS_OSD_SCREENS 1
Dirk Eibachedfe9fe2014-07-03 09:28:17 +0200295#define CONFIG_SYS_DP501_DIFFERENTIAL
296#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
Dirk Eibache50e8962013-07-25 19:28:13 +0200297
298#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
299#define CONFIG_BITBANGMII_MULTI
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100300
Dirk Eibacha605ea72010-10-21 10:50:05 +0200301#endif /* __CONFIG_H */