blob: 18da138507c9db79d2bcf6e34e203c89425a69b1 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stephen Warren73dd5c42016-08-08 09:41:34 -06002/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
Stephen Warren73dd5c42016-08-08 09:41:34 -06004 */
5
6#include <common.h>
7#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06008#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -07009#include <malloc.h>
Simon Glass10453152019-11-14 12:57:30 -070010#include <time.h>
Stephen Warren73dd5c42016-08-08 09:41:34 -060011#include <dm/lists.h>
12#include <dm/root.h>
13#include <mailbox.h>
14#include <misc.h>
15#include <asm/arch-tegra/bpmp_abi.h>
16#include <asm/arch-tegra/ivc.h>
Simon Glasscd93d622020-05-10 11:40:13 -060017#include <linux/bitops.h>
Simon Glass61b29b82020-02-03 07:36:15 -070018#include <linux/err.h>
Stephen Warren73dd5c42016-08-08 09:41:34 -060019
20#define BPMP_IVC_FRAME_COUNT 1
21#define BPMP_IVC_FRAME_SIZE 128
22
23#define BPMP_FLAG_DO_ACK BIT(0)
24#define BPMP_FLAG_RING_DOORBELL BIT(1)
25
26DECLARE_GLOBAL_DATA_PTR;
27
28struct tegra186_bpmp {
29 struct mbox_chan mbox;
30 struct tegra_ivc ivc;
31};
32
33static int tegra186_bpmp_call(struct udevice *dev, int mrq, void *tx_msg,
34 int tx_size, void *rx_msg, int rx_size)
35{
36 struct tegra186_bpmp *priv = dev_get_priv(dev);
37 int ret, err;
38 void *ivc_frame;
39 struct mrq_request *req;
40 struct mrq_response *resp;
41 ulong start_time;
42
43 debug("%s(dev=%p, mrq=%u, tx_msg=%p, tx_size=%d, rx_msg=%p, rx_size=%d) (priv=%p)\n",
44 __func__, dev, mrq, tx_msg, tx_size, rx_msg, rx_size, priv);
45
46 if ((tx_size > BPMP_IVC_FRAME_SIZE) || (rx_size > BPMP_IVC_FRAME_SIZE))
47 return -EINVAL;
48
49 ret = tegra_ivc_write_get_next_frame(&priv->ivc, &ivc_frame);
50 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090051 pr_err("tegra_ivc_write_get_next_frame() failed: %d\n", ret);
Stephen Warren73dd5c42016-08-08 09:41:34 -060052 return ret;
53 }
54
55 req = ivc_frame;
56 req->mrq = mrq;
57 req->flags = BPMP_FLAG_DO_ACK | BPMP_FLAG_RING_DOORBELL;
58 memcpy(req + 1, tx_msg, tx_size);
59
60 ret = tegra_ivc_write_advance(&priv->ivc);
61 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090062 pr_err("tegra_ivc_write_advance() failed: %d\n", ret);
Stephen Warren73dd5c42016-08-08 09:41:34 -060063 return ret;
64 }
65
66 start_time = timer_get_us();
67 for (;;) {
68 ret = tegra_ivc_channel_notified(&priv->ivc);
69 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090070 pr_err("tegra_ivc_channel_notified() failed: %d\n", ret);
Stephen Warren73dd5c42016-08-08 09:41:34 -060071 return ret;
72 }
73
74 ret = tegra_ivc_read_get_next_frame(&priv->ivc, &ivc_frame);
75 if (!ret)
76 break;
77
78 /* Timeout 20ms; roughly 10x current max observed duration */
79 if ((timer_get_us() - start_time) > 20 * 1000) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090080 pr_err("tegra_ivc_read_get_next_frame() timed out (%d)\n",
Stephen Warren73dd5c42016-08-08 09:41:34 -060081 ret);
82 return -ETIMEDOUT;
83 }
84 }
85
86 resp = ivc_frame;
87 err = resp->err;
88 if (!err && rx_msg && rx_size)
89 memcpy(rx_msg, resp + 1, rx_size);
90
91 ret = tegra_ivc_read_advance(&priv->ivc);
92 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090093 pr_err("tegra_ivc_write_advance() failed: %d\n", ret);
Stephen Warren73dd5c42016-08-08 09:41:34 -060094 return ret;
95 }
96
97 if (err) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +090098 pr_err("BPMP responded with error %d\n", err);
Stephen Warren73dd5c42016-08-08 09:41:34 -060099 /* err isn't a U-Boot error code, so don't that */
100 return -EIO;
101 }
102
103 return rx_size;
104}
105
106/**
107 * The BPMP exposes multiple different services. We create a sub-device for
108 * each separate type of service, since each device must be of the appropriate
109 * UCLASS.
110 */
111static int tegra186_bpmp_bind(struct udevice *dev)
112{
113 int ret;
114 struct udevice *child;
115
116 debug("%s(dev=%p)\n", __func__, dev);
117
118 ret = device_bind_driver_to_node(dev, "tegra186_clk", "tegra186_clk",
Simon Glass45a26862017-05-18 20:09:07 -0600119 dev_ofnode(dev), &child);
Stephen Warren73dd5c42016-08-08 09:41:34 -0600120 if (ret)
121 return ret;
122
123 ret = device_bind_driver_to_node(dev, "tegra186_reset",
Simon Glass45a26862017-05-18 20:09:07 -0600124 "tegra186_reset", dev_ofnode(dev),
Stephen Warren73dd5c42016-08-08 09:41:34 -0600125 &child);
126 if (ret)
127 return ret;
128
129 ret = device_bind_driver_to_node(dev, "tegra186_power_domain",
130 "tegra186_power_domain",
Simon Glass45a26862017-05-18 20:09:07 -0600131 dev_ofnode(dev), &child);
Stephen Warren73dd5c42016-08-08 09:41:34 -0600132 if (ret)
133 return ret;
134
135 ret = dm_scan_fdt_dev(dev);
136 if (ret)
137 return ret;
138
139 return 0;
140}
141
142static ulong tegra186_bpmp_get_shmem(struct udevice *dev, int index)
143{
144 int ret;
145 struct fdtdec_phandle_args args;
146 fdt_addr_t reg;
147
Simon Glasse160f7d2017-01-17 16:52:55 -0700148 ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
Stephen Warren73dd5c42016-08-08 09:41:34 -0600149 "shmem", NULL, 0, index, &args);
150 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900151 pr_err("fdtdec_parse_phandle_with_args() failed: %d\n", ret);
Stephen Warren73dd5c42016-08-08 09:41:34 -0600152 return ret;
153 }
154
155 reg = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, args.node,
156 "reg", 0, NULL, true);
157 if (reg == FDT_ADDR_T_NONE) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900158 pr_err("fdtdec_get_addr_size_auto_noparent() failed\n");
Stephen Warren73dd5c42016-08-08 09:41:34 -0600159 return -ENODEV;
160 }
161
162 return reg;
163}
164
165static void tegra186_bpmp_ivc_notify(struct tegra_ivc *ivc)
166{
167 struct tegra186_bpmp *priv =
168 container_of(ivc, struct tegra186_bpmp, ivc);
169 int ret;
170
171 ret = mbox_send(&priv->mbox, NULL);
172 if (ret)
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900173 pr_err("mbox_send() failed: %d\n", ret);
Stephen Warren73dd5c42016-08-08 09:41:34 -0600174}
175
176static int tegra186_bpmp_probe(struct udevice *dev)
177{
178 struct tegra186_bpmp *priv = dev_get_priv(dev);
179 int ret;
180 ulong tx_base, rx_base, start_time;
181
182 debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
183
184 ret = mbox_get_by_index(dev, 0, &priv->mbox);
185 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900186 pr_err("mbox_get_by_index() failed: %d\n", ret);
Stephen Warren73dd5c42016-08-08 09:41:34 -0600187 return ret;
188 }
189
190 tx_base = tegra186_bpmp_get_shmem(dev, 0);
191 if (IS_ERR_VALUE(tx_base)) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900192 pr_err("tegra186_bpmp_get_shmem failed for tx_base\n");
Stephen Warren73dd5c42016-08-08 09:41:34 -0600193 return tx_base;
194 }
195 rx_base = tegra186_bpmp_get_shmem(dev, 1);
196 if (IS_ERR_VALUE(rx_base)) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900197 pr_err("tegra186_bpmp_get_shmem failed for rx_base\n");
Stephen Warren73dd5c42016-08-08 09:41:34 -0600198 return rx_base;
199 }
200 debug("shmem: rx=%lx, tx=%lx\n", rx_base, tx_base);
201
202 ret = tegra_ivc_init(&priv->ivc, rx_base, tx_base, BPMP_IVC_FRAME_COUNT,
203 BPMP_IVC_FRAME_SIZE, tegra186_bpmp_ivc_notify);
204 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900205 pr_err("tegra_ivc_init() failed: %d\n", ret);
Stephen Warren73dd5c42016-08-08 09:41:34 -0600206 return ret;
207 }
208
209 tegra_ivc_channel_reset(&priv->ivc);
210 start_time = timer_get_us();
211 for (;;) {
212 ret = tegra_ivc_channel_notified(&priv->ivc);
213 if (!ret)
214 break;
215
216 /* Timeout 100ms */
217 if ((timer_get_us() - start_time) > 100 * 1000) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900218 pr_err("Initial IVC reset timed out (%d)\n", ret);
Stephen Warren73dd5c42016-08-08 09:41:34 -0600219 ret = -ETIMEDOUT;
220 goto err_free_mbox;
221 }
222 }
223
224 return 0;
225
226err_free_mbox:
227 mbox_free(&priv->mbox);
228
229 return ret;
230}
231
232static int tegra186_bpmp_remove(struct udevice *dev)
233{
234 struct tegra186_bpmp *priv = dev_get_priv(dev);
235
236 debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
237
238 mbox_free(&priv->mbox);
239
240 return 0;
241}
242
243static struct misc_ops tegra186_bpmp_ops = {
244 .call = tegra186_bpmp_call,
245};
246
247static const struct udevice_id tegra186_bpmp_ids[] = {
248 { .compatible = "nvidia,tegra186-bpmp" },
249 { }
250};
251
252U_BOOT_DRIVER(tegra186_bpmp) = {
253 .name = "tegra186_bpmp",
254 .id = UCLASS_MISC,
255 .of_match = tegra186_bpmp_ids,
256 .bind = tegra186_bpmp_bind,
257 .probe = tegra186_bpmp_probe,
258 .remove = tegra186_bpmp_remove,
259 .ops = &tegra186_bpmp_ops,
260 .priv_auto_alloc_size = sizeof(struct tegra186_bpmp),
261};