blob: cd4d32959a0dfbff07bfee46b661a25bb8cf4915 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Thomas Chou38a0f362015-11-09 14:56:02 +08002/*
3 * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
Thomas Chou38a0f362015-11-09 14:56:02 +08004 */
5
6#include <common.h>
Thomas Chou8e8106d2015-12-23 21:47:02 +08007#include <console.h>
Thomas Chou38a0f362015-11-09 14:56:02 +08008#include <dm.h>
9#include <errno.h>
10#include <fdt_support.h>
11#include <flash.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Thomas Chou38a0f362015-11-09 14:56:02 +080013#include <mtd.h>
14#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060015#include <linux/bitops.h>
Thomas Chou38a0f362015-11-09 14:56:02 +080016
17DECLARE_GLOBAL_DATA_PTR;
18
Thomas Chou421f3062015-12-01 17:00:22 +080019/* The STATUS register */
20#define QUADSPI_SR_BP0 BIT(2)
21#define QUADSPI_SR_BP1 BIT(3)
22#define QUADSPI_SR_BP2 BIT(4)
23#define QUADSPI_SR_BP2_0 GENMASK(4, 2)
24#define QUADSPI_SR_BP3 BIT(6)
25#define QUADSPI_SR_TB BIT(5)
26
Thomas Chou38a0f362015-11-09 14:56:02 +080027/*
28 * The QUADSPI_MEM_OP register is used to do memory protect and erase operations
29 */
30#define QUADSPI_MEM_OP_BULK_ERASE 0x00000001
31#define QUADSPI_MEM_OP_SECTOR_ERASE 0x00000002
32#define QUADSPI_MEM_OP_SECTOR_PROTECT 0x00000003
33
34/*
35 * The QUADSPI_ISR register is used to determine whether an invalid write or
36 * erase operation trigerred an interrupt
37 */
38#define QUADSPI_ISR_ILLEGAL_ERASE BIT(0)
39#define QUADSPI_ISR_ILLEGAL_WRITE BIT(1)
40
41struct altera_qspi_regs {
42 u32 rd_status;
43 u32 rd_sid;
44 u32 rd_rdid;
45 u32 mem_op;
46 u32 isr;
47 u32 imr;
48 u32 chip_select;
49};
50
51struct altera_qspi_platdata {
52 struct altera_qspi_regs *regs;
53 void *base;
54 unsigned long size;
55};
56
Thomas Choud579d382015-12-23 20:41:49 +080057static uint flash_verbose;
Thomas Chou38a0f362015-11-09 14:56:02 +080058flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
59
Thomas Chou421f3062015-12-01 17:00:22 +080060static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
61 uint64_t *len);
62
Thomas Chou38a0f362015-11-09 14:56:02 +080063void flash_print_info(flash_info_t *info)
64{
Thomas Chou421f3062015-12-01 17:00:22 +080065 struct mtd_info *mtd = info->mtd;
66 loff_t ofs;
67 u64 len;
68
Thomas Chou38a0f362015-11-09 14:56:02 +080069 printf("Altera QSPI flash Size: %ld MB in %d Sectors\n",
70 info->size >> 20, info->sector_count);
Thomas Chou421f3062015-12-01 17:00:22 +080071 altera_qspi_get_locked_range(mtd, &ofs, &len);
72 printf(" %08lX +%lX", info->start[0], info->size);
73 if (len) {
74 printf(", protected %08llX +%llX",
75 info->start[0] + ofs, len);
76 }
77 putc('\n');
Thomas Chou38a0f362015-11-09 14:56:02 +080078}
79
Thomas Choud579d382015-12-23 20:41:49 +080080void flash_set_verbose(uint v)
81{
82 flash_verbose = v;
83}
84
Thomas Chou38a0f362015-11-09 14:56:02 +080085int flash_erase(flash_info_t *info, int s_first, int s_last)
86{
87 struct mtd_info *mtd = info->mtd;
88 struct erase_info instr;
89 int ret;
90
91 memset(&instr, 0, sizeof(instr));
Thomas Chou1c0e84c2015-12-18 21:35:08 +080092 instr.mtd = mtd;
Thomas Chou38a0f362015-11-09 14:56:02 +080093 instr.addr = mtd->erasesize * s_first;
94 instr.len = mtd->erasesize * (s_last + 1 - s_first);
Thomas Choud579d382015-12-23 20:41:49 +080095 flash_set_verbose(1);
Thomas Chou38a0f362015-11-09 14:56:02 +080096 ret = mtd_erase(mtd, &instr);
Thomas Choud579d382015-12-23 20:41:49 +080097 flash_set_verbose(0);
Thomas Chou38a0f362015-11-09 14:56:02 +080098 if (ret)
Thomas Chouf118fe52015-12-01 16:18:20 +080099 return ERR_PROTECTED;
Thomas Chou38a0f362015-11-09 14:56:02 +0800100
Thomas Choud579d382015-12-23 20:41:49 +0800101 puts(" done\n");
Thomas Chou38a0f362015-11-09 14:56:02 +0800102 return 0;
103}
104
105int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
106{
107 struct mtd_info *mtd = info->mtd;
108 struct udevice *dev = mtd->dev;
109 struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
110 ulong base = (ulong)pdata->base;
111 loff_t to = addr - base;
112 size_t retlen;
113 int ret;
114
115 ret = mtd_write(mtd, to, cnt, &retlen, src);
116 if (ret)
Thomas Chouf118fe52015-12-01 16:18:20 +0800117 return ERR_PROTECTED;
Thomas Chou38a0f362015-11-09 14:56:02 +0800118
119 return 0;
120}
121
122unsigned long flash_init(void)
123{
124 struct udevice *dev;
125
126 /* probe every MTD device */
127 for (uclass_first_device(UCLASS_MTD, &dev);
128 dev;
129 uclass_next_device(&dev)) {
130 }
131
132 return flash_info[0].size;
133}
134
135static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info *instr)
136{
137 struct udevice *dev = mtd->dev;
138 struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
139 struct altera_qspi_regs *regs = pdata->regs;
140 size_t addr = instr->addr;
141 size_t len = instr->len;
142 size_t end = addr + len;
143 u32 sect;
144 u32 stat;
Thomas Chouf81a6732015-12-23 10:33:52 +0800145 u32 *flash, *last;
Thomas Chou38a0f362015-11-09 14:56:02 +0800146
147 instr->state = MTD_ERASING;
148 addr &= ~(mtd->erasesize - 1); /* get lower aligned address */
149 while (addr < end) {
Thomas Chou8e8106d2015-12-23 21:47:02 +0800150 if (ctrlc()) {
151 if (flash_verbose)
152 putc('\n');
153 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
154 instr->state = MTD_ERASE_FAILED;
155 mtd_erase_callback(instr);
156 return -EIO;
157 }
Thomas Chouf81a6732015-12-23 10:33:52 +0800158 flash = pdata->base + addr;
159 last = pdata->base + addr + mtd->erasesize;
160 /* skip erase if sector is blank */
161 while (flash < last) {
162 if (readl(flash) != 0xffffffff)
163 break;
164 flash++;
165 }
166 if (flash < last) {
167 sect = addr / mtd->erasesize;
168 sect <<= 8;
169 sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
170 debug("erase %08x\n", sect);
171 writel(sect, &regs->mem_op);
172 stat = readl(&regs->isr);
173 if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
174 /* erase failed, sector might be protected */
175 debug("erase %08x fail %x\n", sect, stat);
176 writel(stat, &regs->isr); /* clear isr */
177 instr->fail_addr = addr;
178 instr->state = MTD_ERASE_FAILED;
179 mtd_erase_callback(instr);
180 return -EIO;
181 }
Thomas Choud579d382015-12-23 20:41:49 +0800182 if (flash_verbose)
183 putc('.');
184 } else {
185 if (flash_verbose)
186 putc(',');
Thomas Chou38a0f362015-11-09 14:56:02 +0800187 }
188 addr += mtd->erasesize;
189 }
190 instr->state = MTD_ERASE_DONE;
191 mtd_erase_callback(instr);
192
193 return 0;
194}
195
196static int altera_qspi_read(struct mtd_info *mtd, loff_t from, size_t len,
197 size_t *retlen, u_char *buf)
198{
199 struct udevice *dev = mtd->dev;
200 struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
201
202 memcpy_fromio(buf, pdata->base + from, len);
203 *retlen = len;
204
205 return 0;
206}
207
208static int altera_qspi_write(struct mtd_info *mtd, loff_t to, size_t len,
209 size_t *retlen, const u_char *buf)
210{
211 struct udevice *dev = mtd->dev;
212 struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
213 struct altera_qspi_regs *regs = pdata->regs;
214 u32 stat;
215
216 memcpy_toio(pdata->base + to, buf, len);
217 /* check whether write triggered a illegal write interrupt */
218 stat = readl(&regs->isr);
219 if (stat & QUADSPI_ISR_ILLEGAL_WRITE) {
220 /* write failed, sector might be protected */
221 debug("write fail %x\n", stat);
222 writel(stat, &regs->isr); /* clear isr */
223 return -EIO;
224 }
225 *retlen = len;
226
227 return 0;
228}
229
230static void altera_qspi_sync(struct mtd_info *mtd)
231{
232}
233
Thomas Chou421f3062015-12-01 17:00:22 +0800234static void altera_qspi_get_locked_range(struct mtd_info *mtd, loff_t *ofs,
235 uint64_t *len)
236{
237 struct udevice *dev = mtd->dev;
238 struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
239 struct altera_qspi_regs *regs = pdata->regs;
240 int shift0 = ffs(QUADSPI_SR_BP2_0) - 1;
241 int shift3 = ffs(QUADSPI_SR_BP3) - 1 - 3;
242 u32 stat = readl(&regs->rd_status);
243 unsigned pow = ((stat & QUADSPI_SR_BP2_0) >> shift0) |
244 ((stat & QUADSPI_SR_BP3) >> shift3);
245
246 *ofs = 0;
247 *len = 0;
248 if (pow) {
249 *len = mtd->erasesize << (pow - 1);
250 if (*len > mtd->size)
251 *len = mtd->size;
252 if (!(stat & QUADSPI_SR_TB))
253 *ofs = mtd->size - *len;
254 }
255}
256
257static int altera_qspi_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
258{
259 struct udevice *dev = mtd->dev;
260 struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
261 struct altera_qspi_regs *regs = pdata->regs;
262 u32 sector_start, sector_end;
263 u32 num_sectors;
264 u32 mem_op;
265 u32 sr_bp;
266 u32 sr_tb;
267
268 num_sectors = mtd->size / mtd->erasesize;
269 sector_start = ofs / mtd->erasesize;
270 sector_end = (ofs + len) / mtd->erasesize;
271
272 if (sector_start >= num_sectors / 2) {
273 sr_bp = fls(num_sectors - 1 - sector_start) + 1;
274 sr_tb = 0;
275 } else if (sector_end < num_sectors / 2) {
276 sr_bp = fls(sector_end) + 1;
277 sr_tb = 1;
278 } else {
279 sr_bp = 15;
280 sr_tb = 0;
281 }
282
283 mem_op = (sr_tb << 12) | (sr_bp << 8);
284 mem_op |= QUADSPI_MEM_OP_SECTOR_PROTECT;
285 debug("lock %08x\n", mem_op);
286 writel(mem_op, &regs->mem_op);
287
288 return 0;
289}
290
291static int altera_qspi_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
292{
293 struct udevice *dev = mtd->dev;
294 struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
295 struct altera_qspi_regs *regs = pdata->regs;
296 u32 mem_op;
297
298 mem_op = QUADSPI_MEM_OP_SECTOR_PROTECT;
299 debug("unlock %08x\n", mem_op);
300 writel(mem_op, &regs->mem_op);
301
302 return 0;
303}
304
Thomas Chou38a0f362015-11-09 14:56:02 +0800305static int altera_qspi_probe(struct udevice *dev)
306{
307 struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
308 struct altera_qspi_regs *regs = pdata->regs;
309 unsigned long base = (unsigned long)pdata->base;
310 struct mtd_info *mtd;
311 flash_info_t *flash = &flash_info[0];
312 u32 rdid;
313 int i;
314
315 rdid = readl(&regs->rd_rdid);
316 debug("rdid %x\n", rdid);
317
318 mtd = dev_get_uclass_priv(dev);
319 mtd->dev = dev;
320 mtd->name = "nor0";
321 mtd->type = MTD_NORFLASH;
322 mtd->flags = MTD_CAP_NORFLASH;
323 mtd->size = 1 << ((rdid & 0xff) - 6);
324 mtd->writesize = 1;
325 mtd->writebufsize = mtd->writesize;
326 mtd->_erase = altera_qspi_erase;
327 mtd->_read = altera_qspi_read;
328 mtd->_write = altera_qspi_write;
329 mtd->_sync = altera_qspi_sync;
Thomas Chou421f3062015-12-01 17:00:22 +0800330 mtd->_lock = altera_qspi_lock;
331 mtd->_unlock = altera_qspi_unlock;
Thomas Chou38a0f362015-11-09 14:56:02 +0800332 mtd->numeraseregions = 0;
333 mtd->erasesize = 0x10000;
334 if (add_mtd_device(mtd))
335 return -ENOMEM;
336
337 flash->mtd = mtd;
338 flash->size = mtd->size;
339 flash->sector_count = mtd->size / mtd->erasesize;
340 flash->flash_id = rdid;
341 flash->start[0] = base;
342 for (i = 1; i < flash->sector_count; i++)
343 flash->start[i] = flash->start[i - 1] + mtd->erasesize;
344 gd->bd->bi_flashstart = base;
345
346 return 0;
347}
348
349static int altera_qspi_ofdata_to_platdata(struct udevice *dev)
350{
351 struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
352 void *blob = (void *)gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -0700353 int node = dev_of_offset(dev);
Thomas Chou38a0f362015-11-09 14:56:02 +0800354 const char *list, *end;
355 const fdt32_t *cell;
356 void *base;
357 unsigned long addr, size;
358 int parent, addrc, sizec;
359 int len, idx;
360
361 /*
362 * decode regs. there are multiple reg tuples, and they need to
363 * match with reg-names.
364 */
365 parent = fdt_parent_offset(blob, node);
Simon Glasseed36602017-05-18 20:09:26 -0600366 fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
Thomas Chou38a0f362015-11-09 14:56:02 +0800367 list = fdt_getprop(blob, node, "reg-names", &len);
368 if (!list)
369 return -ENOENT;
370 end = list + len;
371 cell = fdt_getprop(blob, node, "reg", &len);
372 if (!cell)
373 return -ENOENT;
374 idx = 0;
375 while (list < end) {
376 addr = fdt_translate_address((void *)blob,
377 node, cell + idx);
378 size = fdt_addr_to_cpu(cell[idx + addrc]);
Thomas Chou8ed38fa2015-11-14 11:22:50 +0800379 base = map_physmem(addr, size, MAP_NOCACHE);
Thomas Chou38a0f362015-11-09 14:56:02 +0800380 len = strlen(list);
381 if (strcmp(list, "avl_csr") == 0) {
382 pdata->regs = base;
383 } else if (strcmp(list, "avl_mem") == 0) {
384 pdata->base = base;
385 pdata->size = size;
386 }
387 idx += addrc + sizec;
388 list += (len + 1);
389 }
390
391 return 0;
392}
393
394static const struct udevice_id altera_qspi_ids[] = {
395 { .compatible = "altr,quadspi-1.0" },
396 {}
397};
398
399U_BOOT_DRIVER(altera_qspi) = {
400 .name = "altera_qspi",
401 .id = UCLASS_MTD,
402 .of_match = altera_qspi_ids,
403 .ofdata_to_platdata = altera_qspi_ofdata_to_platdata,
404 .platdata_auto_alloc_size = sizeof(struct altera_qspi_platdata),
405 .probe = altera_qspi_probe,
406};