Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-2009 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * p2020ds board configuration file |
| 25 | * |
| 26 | */ |
| 27 | #ifndef __CONFIG_H |
| 28 | #define __CONFIG_H |
| 29 | |
Kumar Gala | a0f9e0e | 2009-09-10 16:26:37 -0500 | [diff] [blame] | 30 | #ifdef CONFIG_MK_36BIT |
| 31 | #define CONFIG_PHYS_64BIT |
| 32 | #endif |
| 33 | |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 34 | /* High Level Configuration Options */ |
| 35 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 36 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 37 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
| 38 | #define CONFIG_P2020 1 |
| 39 | #define CONFIG_P2020DS 1 |
| 40 | #define CONFIG_MP 1 /* support multiple processors */ |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 41 | |
| 42 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
| 43 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 44 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
| 45 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ |
| 46 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ |
| 47 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
| 48 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
| 49 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 50 | |
| 51 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
Roy Zang | 29c3518 | 2009-06-30 13:56:23 +0800 | [diff] [blame] | 52 | #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 53 | |
| 54 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 55 | #define CONFIG_ENV_OVERWRITE |
| 56 | |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 57 | #ifndef __ASSEMBLY__ |
| 58 | extern unsigned long calculate_board_sys_clk(unsigned long dummy); |
| 59 | extern unsigned long calculate_board_ddr_clk(unsigned long dummy); |
| 60 | /* extern unsigned long get_board_sys_clk(unsigned long dummy); */ |
| 61 | /* extern unsigned long get_board_ddr_clk(unsigned long dummy); */ |
| 62 | #endif |
| 63 | #define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */ |
| 64 | #define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */ |
| 65 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
| 66 | #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq |
| 67 | from ICS307 instead of switches */ |
| 68 | |
| 69 | /* |
| 70 | * These can be toggled for performance analysis, otherwise use default. |
| 71 | */ |
| 72 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 73 | #define CONFIG_BTB /* toggle branch predition */ |
| 74 | |
| 75 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 76 | |
| 77 | #ifdef CONFIG_PHYS_64BIT |
| 78 | #define CONFIG_ADDR_MAP 1 |
| 79 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ |
| 80 | #endif |
| 81 | |
| 82 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
| 83 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff |
| 84 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 85 | |
| 86 | /* |
| 87 | * Base addresses -- Note these are effective addresses where the |
| 88 | * actual resources get mapped (not physical addresses) |
| 89 | */ |
| 90 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 91 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
| 92 | #ifdef CONFIG_PHYS_64BIT |
| 93 | #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ |
| 94 | #else |
| 95 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ |
| 96 | #endif |
| 97 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
| 98 | |
| 99 | #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) |
| 100 | #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) |
| 101 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) |
| 102 | |
| 103 | /* DDR Setup */ |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 104 | #define CONFIG_VERY_BIG_RAM |
| 105 | #define CONFIG_FSL_DDR3 1 |
| 106 | #undef CONFIG_FSL_DDR_INTERACTIVE |
| 107 | |
Wolfgang Denk | 8e5e9b9 | 2009-07-07 22:35:02 +0200 | [diff] [blame] | 108 | /* ECC will be enabled based on perf_mode environment variable */ |
| 109 | /* #define CONFIG_DDR_ECC */ |
| 110 | |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 111 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 112 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 113 | |
| 114 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 115 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 116 | |
| 117 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 118 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 119 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 120 | |
| 121 | /* I2C addresses of SPD EEPROMs */ |
| 122 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ |
| 123 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
| 124 | |
| 125 | /* These are used when DDR doesn't use SPD. */ |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 126 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ |
| 127 | |
| 128 | /* Default settings for "stable" mode */ |
| 129 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F |
| 130 | #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 |
| 131 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
| 132 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 |
| 133 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 |
| 134 | #define CONFIG_SYS_DDR_TIMING_0 0x00330804 |
| 135 | #define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 |
| 136 | #define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 |
| 137 | #define CONFIG_SYS_DDR_MODE_1 0x00421422 |
| 138 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| 139 | #define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 |
| 140 | #define CONFIG_SYS_DDR_INTERVAL 0x61800100 |
| 141 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 142 | #define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 |
| 143 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 |
| 144 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 |
| 145 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 |
| 146 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 |
| 147 | #define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ |
| 148 | #define CONFIG_SYS_DDR_CONTROL2 0x24400011 |
| 149 | #define CONFIG_SYS_DDR_CDR1 0x00040000 |
| 150 | #define CONFIG_SYS_DDR_CDR2 0x00000000 |
| 151 | |
| 152 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d |
| 153 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 |
| 154 | #define CONFIG_SYS_DDR_SBE 0x00010000 |
| 155 | |
| 156 | /* Settings that differ for "performance" mode */ |
| 157 | #define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ |
| 158 | #define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ |
| 159 | #define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 |
| 160 | #define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 |
| 161 | #define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce |
| 162 | #define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ |
| 163 | |
| 164 | /* |
| 165 | * The following set of values were tested for DDR2 |
| 166 | * with a DDR3 to DDR2 interposer |
| 167 | * |
| 168 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 169 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
| 170 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 |
| 171 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 |
| 172 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 |
| 173 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
| 174 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 |
| 175 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
| 176 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 |
| 177 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 |
| 178 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
| 179 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 |
| 180 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 |
| 181 | * |
| 182 | */ |
| 183 | |
| 184 | #undef CONFIG_CLOCKS_IN_MHZ |
| 185 | |
| 186 | /* |
| 187 | * Memory map |
| 188 | * |
| 189 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| 190 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable |
| 191 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable |
| 192 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable |
| 193 | * |
| 194 | * Localbus cacheable (TBD) |
| 195 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable |
| 196 | * |
| 197 | * Localbus non-cacheable |
| 198 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable |
| 199 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
| 200 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
| 201 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 202 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 |
| 203 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable |
| 204 | */ |
| 205 | |
| 206 | /* |
| 207 | * Local Bus Definitions |
| 208 | */ |
| 209 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
| 210 | #ifdef CONFIG_PHYS_64BIT |
| 211 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull |
| 212 | #else |
| 213 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 214 | #endif |
| 215 | |
| 216 | #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) |
| 217 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
| 218 | |
| 219 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
| 220 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
| 221 | |
| 222 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} |
| 223 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 224 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 225 | |
| 226 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 227 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 228 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 229 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 230 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 231 | |
| 232 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 233 | |
| 234 | #define CONFIG_FLASH_CFI_DRIVER |
| 235 | #define CONFIG_SYS_FLASH_CFI |
| 236 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
| 237 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 |
| 238 | |
| 239 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ |
| 240 | |
Timur Tabi | 5a46960 | 2010-04-01 10:49:42 -0500 | [diff] [blame] | 241 | #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ |
| 242 | |
| 243 | #ifdef CONFIG_FSL_NGPIXIS |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 244 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ |
| 245 | #ifdef CONFIG_PHYS_64BIT |
| 246 | #define PIXIS_BASE_PHYS 0xfffdf0000ull |
| 247 | #else |
| 248 | #define PIXIS_BASE_PHYS PIXIS_BASE |
| 249 | #endif |
| 250 | |
| 251 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
| 252 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
| 253 | |
Timur Tabi | 5a46960 | 2010-04-01 10:49:42 -0500 | [diff] [blame] | 254 | #define PIXIS_LBMAP_SWITCH 7 |
| 255 | #define PIXIS_LBMAP_MASK 0xf0 |
| 256 | #define PIXIS_LBMAP_SHIFT 4 |
| 257 | #define PIXIS_LBMAP_ALTBANK 0x20 |
| 258 | #endif |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 259 | |
| 260 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 261 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ |
| 262 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ |
| 263 | |
| 264 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 265 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) |
| 266 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 267 | |
| 268 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 269 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
| 270 | |
| 271 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| 272 | #ifdef CONFIG_PHYS_64BIT |
| 273 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull |
| 274 | #else |
| 275 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
| 276 | #endif |
| 277 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| 278 | CONFIG_SYS_NAND_BASE + 0x40000, \ |
| 279 | CONFIG_SYS_NAND_BASE + 0x80000,\ |
| 280 | CONFIG_SYS_NAND_BASE + 0xC0000} |
| 281 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 |
| 282 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 283 | #define CONFIG_CMD_NAND 1 |
| 284 | #define CONFIG_NAND_FSL_ELBC 1 |
| 285 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
| 286 | |
| 287 | /* NAND flash config */ |
| 288 | #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
| 289 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 290 | | BR_PS_8 /* Port Size = 8bit */ \ |
| 291 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 292 | | BR_V) /* valid */ |
| 293 | #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
| 294 | | OR_FCM_PGS /* Large Page*/ \ |
| 295 | | OR_FCM_CSCT \ |
| 296 | | OR_FCM_CST \ |
| 297 | | OR_FCM_CHT \ |
| 298 | | OR_FCM_SCY_1 \ |
| 299 | | OR_FCM_TRLX \ |
| 300 | | OR_FCM_EHTR) |
| 301 | |
| 302 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
| 303 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ |
| 304 | #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ |
| 305 | #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ |
| 306 | |
| 307 | #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ |
| 308 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 309 | | BR_PS_8 /* Port Size = 8bit */ \ |
| 310 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 311 | | BR_V) /* valid */ |
| 312 | #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ |
| 313 | #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ |
| 314 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 315 | | BR_PS_8 /* Port Size = 8bit */ \ |
| 316 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 317 | | BR_V) /* valid */ |
| 318 | #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ |
| 319 | |
| 320 | #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ |
| 321 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
| 322 | | BR_PS_8 /* Port Size = 8bit */ \ |
| 323 | | BR_MS_FCM /* MSEL = FCM */ \ |
| 324 | | BR_V) /* valid */ |
| 325 | #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ |
| 326 | |
| 327 | /* Serial Port - controlled on board with jumper J8 |
| 328 | * open - index 2 |
| 329 | * shorted - index 1 |
| 330 | */ |
| 331 | #define CONFIG_CONS_INDEX 1 |
| 332 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
| 333 | #define CONFIG_SYS_NS16550 |
| 334 | #define CONFIG_SYS_NS16550_SERIAL |
| 335 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 336 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| 337 | |
| 338 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 339 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 340 | |
| 341 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 342 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| 343 | |
| 344 | /* Use the HUSH parser */ |
| 345 | #define CONFIG_SYS_HUSH_PARSER |
| 346 | #ifdef CONFIG_SYS_HUSH_PARSER |
| 347 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 348 | #endif |
| 349 | |
| 350 | /* |
| 351 | * Pass open firmware flat tree |
| 352 | */ |
| 353 | #define CONFIG_OF_LIBFDT 1 |
| 354 | #define CONFIG_OF_BOARD_SETUP 1 |
| 355 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| 356 | |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 357 | /* I2C */ |
| 358 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 359 | #define CONFIG_HARD_I2C /* I2C with hardware support */ |
| 360 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 361 | #define CONFIG_I2C_MULTI_BUS |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 362 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 363 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 364 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 365 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ |
| 366 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
| 367 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 |
| 368 | |
| 369 | /* |
| 370 | * I2C2 EEPROM |
| 371 | */ |
| 372 | #define CONFIG_ID_EEPROM |
| 373 | #ifdef CONFIG_ID_EEPROM |
| 374 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 375 | #endif |
| 376 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 377 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 378 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 |
| 379 | |
| 380 | /* |
| 381 | * General PCI |
| 382 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 383 | */ |
| 384 | |
| 385 | /* controller 3, Slot 1, tgtid 3, Base address b000 */ |
| 386 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 |
| 387 | #ifdef CONFIG_PHYS_64BIT |
Kumar Gala | 156984a | 2009-06-18 08:39:42 -0500 | [diff] [blame] | 388 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 389 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull |
| 390 | #else |
| 391 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
| 392 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 |
| 393 | #endif |
| 394 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| 395 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 |
| 396 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 397 | #ifdef CONFIG_PHYS_64BIT |
| 398 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull |
| 399 | #else |
| 400 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
| 401 | #endif |
| 402 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 403 | |
| 404 | /* controller 2, direct to uli, tgtid 2, Base address 9000 */ |
| 405 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
| 406 | #ifdef CONFIG_PHYS_64BIT |
Kumar Gala | 156984a | 2009-06-18 08:39:42 -0500 | [diff] [blame] | 407 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 408 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull |
| 409 | #else |
| 410 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
| 411 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 |
| 412 | #endif |
| 413 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
| 414 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 |
| 415 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 416 | #ifdef CONFIG_PHYS_64BIT |
| 417 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull |
| 418 | #else |
| 419 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
| 420 | #endif |
| 421 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 422 | |
| 423 | /* controller 1, Slot 2, tgtid 1, Base address a000 */ |
| 424 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 |
| 425 | #ifdef CONFIG_PHYS_64BIT |
Kumar Gala | 156984a | 2009-06-18 08:39:42 -0500 | [diff] [blame] | 426 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 427 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull |
| 428 | #else |
| 429 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
| 430 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 |
| 431 | #endif |
| 432 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 433 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 |
| 434 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 435 | #ifdef CONFIG_PHYS_64BIT |
| 436 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull |
| 437 | #else |
| 438 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
| 439 | #endif |
| 440 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 441 | |
| 442 | #if defined(CONFIG_PCI) |
| 443 | |
| 444 | /*PCIE video card used*/ |
| 445 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT |
| 446 | |
| 447 | /* video */ |
| 448 | #define CONFIG_VIDEO |
| 449 | |
| 450 | #if defined(CONFIG_VIDEO) |
| 451 | #define CONFIG_BIOSEMU |
| 452 | #define CONFIG_CFB_CONSOLE |
| 453 | #define CONFIG_VIDEO_SW_CURSOR |
| 454 | #define CONFIG_VGA_AS_SINGLE_DEVICE |
| 455 | #define CONFIG_ATI_RADEON_FB |
| 456 | #define CONFIG_VIDEO_LOGO |
| 457 | /*#define CONFIG_CONSOLE_CURSOR*/ |
| 458 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
| 459 | #endif |
| 460 | |
| 461 | #define CONFIG_NET_MULTI |
| 462 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 463 | |
| 464 | #undef CONFIG_EEPRO100 |
| 465 | #undef CONFIG_TULIP |
| 466 | #define CONFIG_RTL8139 |
| 467 | |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 468 | #ifndef CONFIG_PCI_PNP |
| 469 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS |
| 470 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS |
| 471 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 472 | #endif |
| 473 | |
| 474 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 475 | #define CONFIG_DOS_PARTITION |
| 476 | #define CONFIG_SCSI_AHCI |
| 477 | |
| 478 | #ifdef CONFIG_SCSI_AHCI |
| 479 | #define CONFIG_SATA_ULI5288 |
| 480 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 481 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 482 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) |
| 483 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE |
| 484 | #endif /* SCSI */ |
| 485 | |
| 486 | #endif /* CONFIG_PCI */ |
| 487 | |
| 488 | |
| 489 | #if defined(CONFIG_TSEC_ENET) |
| 490 | |
| 491 | #ifndef CONFIG_NET_MULTI |
| 492 | #define CONFIG_NET_MULTI 1 |
| 493 | #endif |
| 494 | |
| 495 | #define CONFIG_MII 1 /* MII PHY management */ |
| 496 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| 497 | #define CONFIG_TSEC1 1 |
| 498 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 499 | #define CONFIG_TSEC2 1 |
| 500 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| 501 | #define CONFIG_TSEC3 1 |
| 502 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 503 | |
| 504 | #define CONFIG_PIXIS_SGMII_CMD |
| 505 | #define CONFIG_FSL_SGMII_RISER 1 |
| 506 | #define SGMII_RISER_PHY_OFFSET 0x1b |
| 507 | |
| 508 | #ifdef CONFIG_FSL_SGMII_RISER |
| 509 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ |
| 510 | #endif |
| 511 | |
| 512 | #define TSEC1_PHY_ADDR 0 |
| 513 | #define TSEC2_PHY_ADDR 1 |
| 514 | #define TSEC3_PHY_ADDR 2 |
| 515 | |
| 516 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 517 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 518 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 519 | |
| 520 | #define TSEC1_PHYIDX 0 |
| 521 | #define TSEC2_PHYIDX 0 |
| 522 | #define TSEC3_PHYIDX 0 |
| 523 | |
| 524 | #define CONFIG_ETHPRIME "eTSEC1" |
| 525 | |
| 526 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| 527 | #endif /* CONFIG_TSEC_ENET */ |
| 528 | |
| 529 | /* |
| 530 | * Environment |
| 531 | */ |
| 532 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 533 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
| 534 | #define CONFIG_ENV_ADDR 0xfff80000 |
| 535 | #else |
| 536 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
| 537 | #endif |
| 538 | #define CONFIG_ENV_SIZE 0x2000 |
| 539 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
| 540 | |
| 541 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 542 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 543 | |
| 544 | /* |
| 545 | * Command line configuration. |
| 546 | */ |
| 547 | #include <config_cmd_default.h> |
| 548 | |
| 549 | #define CONFIG_CMD_IRQ |
| 550 | #define CONFIG_CMD_PING |
| 551 | #define CONFIG_CMD_I2C |
| 552 | #define CONFIG_CMD_MII |
| 553 | #define CONFIG_CMD_ELF |
| 554 | #define CONFIG_CMD_IRQ |
| 555 | #define CONFIG_CMD_SETEXPR |
| 556 | |
| 557 | #if defined(CONFIG_PCI) |
| 558 | #define CONFIG_CMD_PCI |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 559 | #define CONFIG_CMD_NET |
| 560 | #define CONFIG_CMD_SCSI |
| 561 | #define CONFIG_CMD_EXT2 |
| 562 | #endif |
| 563 | |
Roy Zang | 0ead6f2 | 2009-09-10 14:44:48 +0800 | [diff] [blame] | 564 | /* |
| 565 | * USB |
| 566 | */ |
| 567 | #define CONFIG_CMD_USB |
| 568 | #define CONFIG_USB_STORAGE |
| 569 | #define CONFIG_USB_EHCI |
| 570 | #define CONFIG_USB_EHCI_FSL |
| 571 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 572 | |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 573 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 574 | |
| 575 | /* |
| 576 | * Miscellaneous configurable options |
| 577 | */ |
| 578 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 579 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 580 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 581 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
| 582 | #if defined(CONFIG_CMD_KGDB) |
| 583 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 584 | #else |
| 585 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 586 | #endif |
| 587 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 588 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 589 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 590 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 591 | |
| 592 | /* |
| 593 | * For booting Linux, the board info and command line data |
Kumar Gala | 89188a6 | 2009-07-15 08:54:50 -0500 | [diff] [blame] | 594 | * have to be in the first 16 MB of memory, since this is |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 595 | * the maximum mapped by the Linux kernel during initialization. |
| 596 | */ |
Kumar Gala | 89188a6 | 2009-07-15 08:54:50 -0500 | [diff] [blame] | 597 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ |
Srikanth Srinivasan | feb7838 | 2009-04-03 15:36:13 -0500 | [diff] [blame] | 598 | |
| 599 | /* |
| 600 | * Internal Definitions |
| 601 | * |
| 602 | * Boot Flags |
| 603 | */ |
| 604 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 605 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 606 | |
| 607 | #if defined(CONFIG_CMD_KGDB) |
| 608 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 609 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 610 | #endif |
| 611 | |
| 612 | /* |
| 613 | * Environment Configuration |
| 614 | */ |
| 615 | |
| 616 | /* The mac addresses for all ethernet interface */ |
| 617 | #if defined(CONFIG_TSEC_ENET) |
| 618 | #define CONFIG_HAS_ETH0 |
| 619 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD |
| 620 | #define CONFIG_HAS_ETH1 |
| 621 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD |
| 622 | #define CONFIG_HAS_ETH2 |
| 623 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD |
| 624 | #define CONFIG_HAS_ETH3 |
| 625 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD |
| 626 | #endif |
| 627 | |
| 628 | #define CONFIG_IPADDR 192.168.1.254 |
| 629 | |
| 630 | #define CONFIG_HOSTNAME unknown |
| 631 | #define CONFIG_ROOTPATH /opt/nfsroot |
| 632 | #define CONFIG_BOOTFILE uImage |
| 633 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| 634 | |
| 635 | #define CONFIG_SERVERIP 192.168.1.1 |
| 636 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 637 | #define CONFIG_NETMASK 255.255.255.0 |
| 638 | |
| 639 | /* default location for tftp and bootm */ |
| 640 | #define CONFIG_LOADADDR 1000000 |
| 641 | |
| 642 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
| 643 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 644 | |
| 645 | #define CONFIG_BAUDRATE 115200 |
| 646 | |
| 647 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 648 | "perf_mode=stable\0" \ |
| 649 | "memctl_intlv_ctl=2\0" \ |
| 650 | "netdev=eth0\0" \ |
| 651 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ |
| 652 | "tftpflash=tftpboot $loadaddr $uboot; " \ |
| 653 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 654 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 655 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ |
| 656 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ |
| 657 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ |
| 658 | "consoledev=ttyS0\0" \ |
| 659 | "ramdiskaddr=2000000\0" \ |
| 660 | "ramdiskfile=p2020ds/ramdisk.uboot\0" \ |
| 661 | "fdtaddr=c00000\0" \ |
| 662 | "fdtfile=p2020ds/p2020ds.dtb\0" \ |
| 663 | "bdev=sda3\0" |
| 664 | |
| 665 | #define CONFIG_HDBOOT \ |
| 666 | "setenv bootargs root=/dev/$bdev rw " \ |
| 667 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 668 | "tftp $loadaddr $bootfile;" \ |
| 669 | "tftp $fdtaddr $fdtfile;" \ |
| 670 | "bootm $loadaddr - $fdtaddr" |
| 671 | |
| 672 | #define CONFIG_NFSBOOTCOMMAND \ |
| 673 | "setenv bootargs root=/dev/nfs rw " \ |
| 674 | "nfsroot=$serverip:$rootpath " \ |
| 675 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ |
| 676 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 677 | "tftp $loadaddr $bootfile;" \ |
| 678 | "tftp $fdtaddr $fdtfile;" \ |
| 679 | "bootm $loadaddr - $fdtaddr" |
| 680 | |
| 681 | #define CONFIG_RAMBOOTCOMMAND \ |
| 682 | "setenv bootargs root=/dev/ram rw " \ |
| 683 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 684 | "tftp $ramdiskaddr $ramdiskfile;" \ |
| 685 | "tftp $loadaddr $bootfile;" \ |
| 686 | "tftp $fdtaddr $fdtfile;" \ |
| 687 | "bootm $loadaddr $ramdiskaddr $fdtaddr" |
| 688 | |
| 689 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT |
| 690 | |
| 691 | #endif /* __CONFIG_H */ |