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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
haikunddf79f32015-03-25 20:23:26 +08002/*
3 * Freescale ls1021a SOC common device tree source
4 *
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
haikunddf79f32015-03-25 20:23:26 +08006 */
7
haikunce35fc12015-03-24 21:16:31 +08008#include "skeleton.dtsi"
haikunddf79f32015-03-25 20:23:26 +08009#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 compatible = "fsl,ls1021a";
13 interrupt-parent = <&gic>;
14
15 aliases {
16 serial0 = &lpuart0;
17 serial1 = &lpuart1;
18 serial2 = &lpuart2;
19 serial3 = &lpuart3;
20 serial4 = &lpuart4;
21 serial5 = &lpuart5;
22 sysclk = &sysclk;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@f00 {
30 compatible = "arm,cortex-a7";
31 device_type = "cpu";
32 reg = <0xf00>;
33 clocks = <&cluster1_clk>;
34 };
35
36 cpu@f01 {
37 compatible = "arm,cortex-a7";
38 device_type = "cpu";
39 reg = <0xf01>;
40 clocks = <&cluster1_clk>;
41 };
42 };
43
44 timer {
45 compatible = "arm,armv7-timer";
46 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
47 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
50 };
51
52 pmu {
53 compatible = "arm,cortex-a7-pmu";
54 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
56 };
57
58 soc {
59 compatible = "simple-bus";
haikunce35fc12015-03-24 21:16:31 +080060 #address-cells = <1>;
61 #size-cells = <1>;
haikunddf79f32015-03-25 20:23:26 +080062 device_type = "soc";
63 interrupt-parent = <&gic>;
64 ranges;
65
66 gic: interrupt-controller@1400000 {
67 compatible = "arm,cortex-a7-gic";
68 #interrupt-cells = <3>;
69 interrupt-controller;
haikunce35fc12015-03-24 21:16:31 +080070 reg = <0x1401000 0x1000>,
71 <0x1402000 0x1000>,
72 <0x1404000 0x2000>,
73 <0x1406000 0x2000>;
haikunddf79f32015-03-25 20:23:26 +080074 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
75
76 };
77
78 ifc: ifc@1530000 {
79 compatible = "fsl,ifc", "simple-bus";
haikunce35fc12015-03-24 21:16:31 +080080 reg = <0x1530000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +080081 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
82 };
83
84 dcfg: dcfg@1ee0000 {
85 compatible = "fsl,ls1021a-dcfg", "syscon";
haikunce35fc12015-03-24 21:16:31 +080086 reg = <0x1ee0000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +080087 big-endian;
88 };
89
90 esdhc: esdhc@1560000 {
91 compatible = "fsl,esdhc";
haikunce35fc12015-03-24 21:16:31 +080092 reg = <0x1560000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +080093 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
94 clock-frequency = <0>;
95 voltage-ranges = <1800 1800 3300 3300>;
96 sdhci,auto-cmd12;
97 big-endian;
98 bus-width = <4>;
haikunddf79f32015-03-25 20:23:26 +080099 };
100
Biwen Li2b3393c2021-02-05 19:01:48 +0800101 gpio0: gpio@2300000 {
102 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
Lasse Klok Mikkelsenfb6c96f2021-06-08 08:39:12 +0200103 reg = <0x2300000 0x10000>;
Biwen Li2b3393c2021-02-05 19:01:48 +0800104 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
105 gpio-controller;
106 #gpio-cells = <2>;
107 interrupt-controller;
108 #interrupt-cells = <2>;
109 };
110
111 gpio1: gpio@2310000 {
112 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
Lasse Klok Mikkelsenfb6c96f2021-06-08 08:39:12 +0200113 reg = <0x2310000 0x10000>;
Biwen Li2b3393c2021-02-05 19:01:48 +0800114 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
115 gpio-controller;
116 #gpio-cells = <2>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
119 };
120
121 gpio2: gpio@2320000 {
122 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
Lasse Klok Mikkelsenfb6c96f2021-06-08 08:39:12 +0200123 reg = <0x2320000 0x10000>;
Biwen Li2b3393c2021-02-05 19:01:48 +0800124 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
125 gpio-controller;
126 #gpio-cells = <2>;
127 interrupt-controller;
128 #interrupt-cells = <2>;
129 };
130
131 gpio3: gpio@2330000 {
132 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
Lasse Klok Mikkelsenfb6c96f2021-06-08 08:39:12 +0200133 reg = <0x2330000 0x10000>;
Biwen Li2b3393c2021-02-05 19:01:48 +0800134 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
135 gpio-controller;
136 #gpio-cells = <2>;
137 interrupt-controller;
138 #interrupt-cells = <2>;
139 };
140
haikunddf79f32015-03-25 20:23:26 +0800141 scfg: scfg@1570000 {
142 compatible = "fsl,ls1021a-scfg", "syscon";
haikunce35fc12015-03-24 21:16:31 +0800143 reg = <0x1570000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800144 big-endian;
145 };
146
147 clockgen: clocking@1ee1000 {
148 #address-cells = <1>;
149 #size-cells = <1>;
haikunce35fc12015-03-24 21:16:31 +0800150 ranges = <0x0 0x1ee1000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800151
152 sysclk: sysclk {
153 compatible = "fixed-clock";
154 #clock-cells = <0>;
155 clock-output-names = "sysclk";
156 };
157
158 cga_pll1: pll@800 {
159 compatible = "fsl,qoriq-core-pll-2.0";
160 #clock-cells = <1>;
161 reg = <0x800 0x10>;
162 clocks = <&sysclk>;
163 clock-output-names = "cga-pll1", "cga-pll1-div2",
164 "cga-pll1-div4";
165 };
166
167 platform_clk: pll@c00 {
168 compatible = "fsl,qoriq-core-pll-2.0";
169 #clock-cells = <1>;
170 reg = <0xc00 0x10>;
171 clocks = <&sysclk>;
172 clock-output-names = "platform-clk", "platform-clk-div2";
173 };
174
175 cluster1_clk: clk0c0@0 {
176 compatible = "fsl,qoriq-core-mux-2.0";
177 #clock-cells = <0>;
178 reg = <0x0 0x10>;
179 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
180 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
181 clock-output-names = "cluster1-clk";
182 };
183 };
184
185 dspi0: dspi@2100000 {
186 compatible = "fsl,vf610-dspi";
187 #address-cells = <1>;
188 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800189 reg = <0x2100000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800190 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
191 clock-names = "dspi";
192 clocks = <&platform_clk 1>;
Michael Walle8c580892021-10-13 18:14:18 +0200193 spi-num-chipselects = <6>;
haikunddf79f32015-03-25 20:23:26 +0800194 big-endian;
195 status = "disabled";
196 };
197
198 dspi1: dspi@2110000 {
199 compatible = "fsl,vf610-dspi";
200 #address-cells = <1>;
201 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800202 reg = <0x2110000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800203 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
204 clock-names = "dspi";
205 clocks = <&platform_clk 1>;
Michael Walle8c580892021-10-13 18:14:18 +0200206 spi-num-chipselects = <6>;
haikunddf79f32015-03-25 20:23:26 +0800207 big-endian;
208 status = "disabled";
209 };
210
Haikun.Wang@freescale.com863b4e12015-03-24 21:20:40 +0800211 qspi: quadspi@1550000 {
Kuldeep Singhb480bcc2019-12-12 11:49:24 +0530212 compatible = "fsl,ls1021a-qspi";
Haikun.Wang@freescale.com863b4e12015-03-24 21:20:40 +0800213 #address-cells = <1>;
214 #size-cells = <0>;
215 reg = <0x1550000 0x10000>,
Kuldeep Singhb480bcc2019-12-12 11:49:24 +0530216 <0x40000000 0x1000000>;
Yuan Yao93a1b7c2016-11-30 11:26:20 +0800217 reg-names = "QuadSPI", "QuadSPI-memory";
Haikun.Wang@freescale.com863b4e12015-03-24 21:20:40 +0800218 status = "disabled";
219 };
220
haikunddf79f32015-03-25 20:23:26 +0800221 i2c0: i2c@2180000 {
222 compatible = "fsl,vf610-i2c";
223 #address-cells = <1>;
224 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800225 reg = <0x2180000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800226 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
227 clock-names = "i2c";
228 clocks = <&platform_clk 1>;
229 status = "disabled";
230 };
231
232 i2c1: i2c@2190000 {
233 compatible = "fsl,vf610-i2c";
234 #address-cells = <1>;
235 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800236 reg = <0x2190000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800237 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
238 clock-names = "i2c";
239 clocks = <&platform_clk 1>;
240 status = "disabled";
241 };
242
243 i2c2: i2c@21a0000 {
244 compatible = "fsl,vf610-i2c";
245 #address-cells = <1>;
246 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800247 reg = <0x21a0000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800248 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
249 clock-names = "i2c";
250 clocks = <&platform_clk 1>;
251 status = "disabled";
252 };
253
254 uart0: serial@21c0500 {
255 compatible = "fsl,16550-FIFO64", "ns16550a";
haikunce35fc12015-03-24 21:16:31 +0800256 reg = <0x21c0500 0x100>;
haikunddf79f32015-03-25 20:23:26 +0800257 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
haikunddf79f32015-03-25 20:23:26 +0800258 fifo-size = <15>;
259 status = "disabled";
260 };
261
262 uart1: serial@21c0600 {
263 compatible = "fsl,16550-FIFO64", "ns16550a";
haikunce35fc12015-03-24 21:16:31 +0800264 reg = <0x21c0600 0x100>;
haikunddf79f32015-03-25 20:23:26 +0800265 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
haikunddf79f32015-03-25 20:23:26 +0800266 fifo-size = <15>;
267 status = "disabled";
268 };
269
270 uart2: serial@21d0500 {
271 compatible = "fsl,16550-FIFO64", "ns16550a";
haikunce35fc12015-03-24 21:16:31 +0800272 reg = <0x21d0500 0x100>;
haikunddf79f32015-03-25 20:23:26 +0800273 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
haikunddf79f32015-03-25 20:23:26 +0800274 fifo-size = <15>;
275 status = "disabled";
276 };
277
278 uart3: serial@21d0600 {
279 compatible = "fsl,16550-FIFO64", "ns16550a";
haikunce35fc12015-03-24 21:16:31 +0800280 reg = <0x21d0600 0x100>;
haikunddf79f32015-03-25 20:23:26 +0800281 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
haikunddf79f32015-03-25 20:23:26 +0800282 fifo-size = <15>;
283 status = "disabled";
284 };
285
286 lpuart0: serial@2950000 {
287 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800288 reg = <0x2950000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800289 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&sysclk>;
291 clock-names = "ipg";
292 status = "disabled";
293 };
294
295 lpuart1: serial@2960000 {
296 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800297 reg = <0x2960000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800298 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&platform_clk 1>;
300 clock-names = "ipg";
301 status = "disabled";
302 };
303
304 lpuart2: serial@2970000 {
305 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800306 reg = <0x2970000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800307 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&platform_clk 1>;
309 clock-names = "ipg";
310 status = "disabled";
311 };
312
313 lpuart3: serial@2980000 {
314 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800315 reg = <0x2980000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800316 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&platform_clk 1>;
318 clock-names = "ipg";
319 status = "disabled";
320 };
321
322 lpuart4: serial@2990000 {
323 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800324 reg = <0x2990000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800325 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&platform_clk 1>;
327 clock-names = "ipg";
328 status = "disabled";
329 };
330
331 lpuart5: serial@29a0000 {
332 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800333 reg = <0x29a0000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800334 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&platform_clk 1>;
336 clock-names = "ipg";
337 status = "disabled";
338 };
339
340 wdog0: watchdog@2ad0000 {
341 compatible = "fsl,imx21-wdt";
haikunce35fc12015-03-24 21:16:31 +0800342 reg = <0x2ad0000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800343 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&platform_clk 1>;
345 clock-names = "wdog-en";
346 big-endian;
347 };
348
349 sai1: sai@2b50000 {
350 compatible = "fsl,vf610-sai";
haikunce35fc12015-03-24 21:16:31 +0800351 reg = <0x2b50000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800352 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&platform_clk 1>;
354 clock-names = "sai";
355 dma-names = "tx", "rx";
356 dmas = <&edma0 1 47>,
357 <&edma0 1 46>;
358 big-endian;
359 status = "disabled";
360 };
361
362 sai2: sai@2b60000 {
363 compatible = "fsl,vf610-sai";
haikunce35fc12015-03-24 21:16:31 +0800364 reg = <0x2b60000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800365 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&platform_clk 1>;
367 clock-names = "sai";
368 dma-names = "tx", "rx";
369 dmas = <&edma0 1 45>,
370 <&edma0 1 44>;
371 big-endian;
372 status = "disabled";
373 };
374
375 edma0: edma@2c00000 {
376 #dma-cells = <2>;
377 compatible = "fsl,vf610-edma";
haikunce35fc12015-03-24 21:16:31 +0800378 reg = <0x2c00000 0x10000>,
379 <0x2c10000 0x10000>,
380 <0x2c20000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800381 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
382 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
383 interrupt-names = "edma-tx", "edma-err";
384 dma-channels = <32>;
385 big-endian;
386 clock-names = "dmamux0", "dmamux1";
387 clocks = <&platform_clk 1>,
388 <&platform_clk 1>;
389 };
390
Bin Mengf588b4d2019-07-19 00:29:59 +0300391 enet0: ethernet@2d10000 {
392 compatible = "fsl,etsec2";
393 reg = <0x2d10000 0x1000>;
394 status = "disabled";
395 };
396
397 enet1: ethernet@2d50000 {
398 compatible = "fsl,etsec2";
399 reg = <0x2d50000 0x1000>;
400 status = "disabled";
401 };
402
403 enet2: ethernet@2d90000 {
404 compatible = "fsl,etsec2";
405 reg = <0x2d90000 0x1000>;
406 status = "disabled";
407 };
408
haikunddf79f32015-03-25 20:23:26 +0800409 mdio0: mdio@2d24000 {
Bin Mengf588b4d2019-07-19 00:29:59 +0300410 compatible = "fsl,etsec2-mdio";
411 reg = <0x2d24000 0x4000>;
haikunddf79f32015-03-25 20:23:26 +0800412 #address-cells = <1>;
413 #size-cells = <0>;
Bin Mengf588b4d2019-07-19 00:29:59 +0300414 };
415
416 mdio1: mdio@2d64000 {
417 compatible = "fsl,etsec2-mdio";
418 reg = <0x2d64000 0x4000>;
419 #address-cells = <1>;
420 #size-cells = <0>;
haikunddf79f32015-03-25 20:23:26 +0800421 };
422
423 usb@8600000 {
424 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
haikunce35fc12015-03-24 21:16:31 +0800425 reg = <0x8600000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800426 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
427 dr_mode = "host";
428 phy_type = "ulpi";
429 };
430
431 usb3@3100000 {
Rajesh Bhagata866c212016-07-01 18:51:48 +0530432 compatible = "fsl,layerscape-dwc3";
haikunce35fc12015-03-24 21:16:31 +0800433 reg = <0x3100000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800434 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
435 dr_mode = "host";
436 };
Minghuan Lianadd73a12016-12-13 14:54:11 +0800437
438 pcie@3400000 {
439 compatible = "fsl,ls-pcie", "snps,dw-pcie";
440 reg = <0x03400000 0x20000 /* dbi registers */
441 0x01570000 0x10000 /* pf controls registers */
442 0x24000000 0x20000>; /* configuration space */
443 reg-names = "dbi", "ctrl", "config";
444 big-endian;
445 #address-cells = <3>;
446 #size-cells = <2>;
447 device_type = "pci";
448 bus-range = <0x0 0xff>;
449 ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000 /* downstream I/O */
450 0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
451 };
452
453 pcie@3500000 {
454 compatible = "fsl,ls-pcie", "snps,dw-pcie";
455 reg = <0x03500000 0x10000 /* dbi registers */
456 0x01570000 0x10000 /* pf controls registers */
457 0x34000000 0x20000>; /* configuration space */
458 reg-names = "dbi", "ctrl", "config";
459 big-endian;
460 #address-cells = <3>;
461 #size-cells = <2>;
462 device_type = "pci";
463 num-lanes = <2>;
464 bus-range = <0x0 0xff>;
465 ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */
466 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
467 };
Peng Ma9ed5ec92018-08-01 14:15:41 +0800468
469 sata: sata@3200000 {
470 compatible = "fsl,ls1021a-ahci";
Peng Maf68ce9e2019-05-29 02:40:47 +0000471 reg = <0x3200000 0x10000 0x20220520 0x4>;
Michael Wallecde9b142021-10-13 18:14:20 +0200472 reg-names = "ahci", "sata-ecc";
Peng Ma9ed5ec92018-08-01 14:15:41 +0800473 interrupts = <0 101 4>;
474 status = "disabled";
475 };
haikunddf79f32015-03-25 20:23:26 +0800476 };
477};