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Michal Simek78d19a32009-09-07 09:08:02 +02001/*
2 * (C) Copyright 2007-2009 Michal Simek
3 * (C) Copyright 2003 Xilinx Inc.
Michal Simek89c53892008-03-28 12:41:56 +01004 *
Michal Simek89c53892008-03-28 12:41:56 +01005 * Michal SIMEK <monstr@monstr.eu>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Michal Simek78d19a32009-09-07 09:08:02 +02008 */
Michal Simek89c53892008-03-28 12:41:56 +01009
10#include <common.h>
11#include <net.h>
12#include <config.h>
Michal Simekd538ee12015-12-10 17:15:52 +010013#include <dm.h>
Michal Simekd722e862015-12-10 13:33:20 +010014#include <console.h>
Michal Simek042272a2010-10-11 11:41:47 +100015#include <malloc.h>
Michal Simek89c53892008-03-28 12:41:56 +010016#include <asm/io.h>
Michal Simekd722e862015-12-10 13:33:20 +010017#include <phy.h>
18#include <miiphy.h>
Michal Simek7fd70822012-06-28 21:37:57 +000019#include <fdtdec.h>
Masahiro Yamada5d97dff2016-09-21 11:28:57 +090020#include <linux/errno.h>
Michal Simek4d2749b2015-12-10 16:31:38 +010021#include <linux/kernel.h>
Zubair Lutfullah Kakakhel39e020e2016-07-27 12:25:07 +010022#include <asm/io.h>
Michal Simek7fd70822012-06-28 21:37:57 +000023
Michal Simekd538ee12015-12-10 17:15:52 +010024DECLARE_GLOBAL_DATA_PTR;
Michal Simek89c53892008-03-28 12:41:56 +010025
Michal Simek89c53892008-03-28 12:41:56 +010026#define ENET_ADDR_LENGTH 6
Michal Simek4d2749b2015-12-10 16:31:38 +010027#define ETH_FCS_LEN 4 /* Octets in the FCS */
Michal Simek89c53892008-03-28 12:41:56 +010028
29/* Xmit complete */
30#define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
31/* Xmit interrupt enable bit */
32#define XEL_TSR_XMIT_IE_MASK 0x00000008UL
Michal Simek89c53892008-03-28 12:41:56 +010033/* Program the MAC address */
34#define XEL_TSR_PROGRAM_MASK 0x00000002UL
35/* define for programming the MAC address into the EMAC Lite */
36#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
37
38/* Transmit packet length upper byte */
39#define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
40/* Transmit packet length lower byte */
41#define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
42
43/* Recv complete */
44#define XEL_RSR_RECV_DONE_MASK 0x00000001UL
45/* Recv interrupt enable bit */
46#define XEL_RSR_RECV_IE_MASK 0x00000008UL
47
Michal Simekd722e862015-12-10 13:33:20 +010048/* MDIO Address Register Bit Masks */
49#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
50#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
51#define XEL_MDIOADDR_PHYADR_SHIFT 5
52#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
53
54/* MDIO Write Data Register Bit Masks */
55#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
56
57/* MDIO Read Data Register Bit Masks */
58#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
59
60/* MDIO Control Register Bit Masks */
61#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
62#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
63
Michal Simek9a23c492015-12-10 14:18:15 +010064struct emaclite_regs {
65 u32 tx_ping; /* 0x0 - TX Ping buffer */
66 u32 reserved1[504];
67 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
68 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
69 u32 mdiord;/* 0x7ec - MDIO Read Data Register */
70 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
71 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
72 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
73 u32 tx_ping_tsr; /* 0x7fc - Tx status */
74 u32 tx_pong; /* 0x800 - TX Pong buffer */
75 u32 reserved2[508];
76 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
77 u32 reserved3; /* 0xff8 */
78 u32 tx_pong_tsr; /* 0xffc - Tx status */
79 u32 rx_ping; /* 0x1000 - Receive Buffer */
80 u32 reserved4[510];
81 u32 rx_ping_rsr; /* 0x17fc - Rx status */
82 u32 rx_pong; /* 0x1800 - Receive Buffer */
83 u32 reserved5[510];
84 u32 rx_pong_rsr; /* 0x1ffc - Rx status */
85};
86
Michal Simek773cfa82011-08-25 12:47:56 +020087struct xemaclite {
Michal Simek4d2749b2015-12-10 16:31:38 +010088 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
Michal Simek947324b2011-09-12 21:10:01 +000089 u32 txpp; /* TX ping pong buffer */
90 u32 rxpp; /* RX ping pong buffer */
Michal Simekd722e862015-12-10 13:33:20 +010091 int phyaddr;
Michal Simek9a23c492015-12-10 14:18:15 +010092 struct emaclite_regs *regs;
Michal Simekd722e862015-12-10 13:33:20 +010093 struct phy_device *phydev;
94 struct mii_dev *bus;
Michal Simek773cfa82011-08-25 12:47:56 +020095};
Michal Simek89c53892008-03-28 12:41:56 +010096
Michal Simekf412b6a2015-12-16 10:52:39 +010097static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
Michal Simek89c53892008-03-28 12:41:56 +010098
Michal Simek5ac83802011-09-12 21:10:05 +000099static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
Michal Simek89c53892008-03-28 12:41:56 +0100100{
Michal Simek042272a2010-10-11 11:41:47 +1000101 u32 i;
Michal Simek89c53892008-03-28 12:41:56 +0100102 u32 alignbuffer;
103 u32 *to32ptr;
104 u32 *from32ptr;
105 u8 *to8ptr;
106 u8 *from8ptr;
107
108 from32ptr = (u32 *) srcptr;
109
110 /* Word aligned buffer, no correction needed. */
111 to32ptr = (u32 *) destptr;
112 while (bytecount > 3) {
113 *to32ptr++ = *from32ptr++;
114 bytecount -= 4;
115 }
116 to8ptr = (u8 *) to32ptr;
117
118 alignbuffer = *from32ptr++;
Michal Simek5ac83802011-09-12 21:10:05 +0000119 from8ptr = (u8 *) &alignbuffer;
Michal Simek89c53892008-03-28 12:41:56 +0100120
Michal Simek5ac83802011-09-12 21:10:05 +0000121 for (i = 0; i < bytecount; i++)
Michal Simek89c53892008-03-28 12:41:56 +0100122 *to8ptr++ = *from8ptr++;
Michal Simek89c53892008-03-28 12:41:56 +0100123}
124
Michal Simek00702512015-12-10 16:01:50 +0100125static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
Michal Simek89c53892008-03-28 12:41:56 +0100126{
Michal Simek042272a2010-10-11 11:41:47 +1000127 u32 i;
Michal Simek89c53892008-03-28 12:41:56 +0100128 u32 alignbuffer;
129 u32 *to32ptr = (u32 *) destptr;
130 u32 *from32ptr;
131 u8 *to8ptr;
132 u8 *from8ptr;
133
134 from32ptr = (u32 *) srcptr;
135 while (bytecount > 3) {
136
137 *to32ptr++ = *from32ptr++;
138 bytecount -= 4;
139 }
140
141 alignbuffer = 0;
Michal Simek5ac83802011-09-12 21:10:05 +0000142 to8ptr = (u8 *) &alignbuffer;
Michal Simek89c53892008-03-28 12:41:56 +0100143 from8ptr = (u8 *) from32ptr;
144
Michal Simek5ac83802011-09-12 21:10:05 +0000145 for (i = 0; i < bytecount; i++)
Michal Simek89c53892008-03-28 12:41:56 +0100146 *to8ptr++ = *from8ptr++;
Michal Simek89c53892008-03-28 12:41:56 +0100147
148 *to32ptr++ = alignbuffer;
149}
150
Michal Simekd722e862015-12-10 13:33:20 +0100151static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
152 bool set, unsigned int timeout)
153{
154 u32 val;
155 unsigned long start = get_timer(0);
156
157 while (1) {
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100158 val = __raw_readl(reg);
Michal Simekd722e862015-12-10 13:33:20 +0100159
160 if (!set)
161 val = ~val;
162
163 if ((val & mask) == mask)
164 return 0;
165
166 if (get_timer(start) > timeout)
167 break;
168
169 if (ctrlc()) {
170 puts("Abort\n");
171 return -EINTR;
172 }
173
174 udelay(1);
175 }
176
177 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
178 func, reg, mask, set);
179
180 return -ETIMEDOUT;
181}
182
Michal Simek9a23c492015-12-10 14:18:15 +0100183static int mdio_wait(struct emaclite_regs *regs)
Michal Simekd722e862015-12-10 13:33:20 +0100184{
Michal Simek9a23c492015-12-10 14:18:15 +0100185 return wait_for_bit(__func__, &regs->mdioctrl,
Michal Simekd722e862015-12-10 13:33:20 +0100186 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
187}
188
Michal Simek9a23c492015-12-10 14:18:15 +0100189static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
Michal Simekd722e862015-12-10 13:33:20 +0100190 u16 *data)
191{
Michal Simek9a23c492015-12-10 14:18:15 +0100192 struct emaclite_regs *regs = emaclite->regs;
193
194 if (mdio_wait(regs))
Michal Simekd722e862015-12-10 13:33:20 +0100195 return 1;
196
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100197 u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
198 __raw_writel(XEL_MDIOADDR_OP_MASK
199 | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
200 | registernum), &regs->mdioaddr);
201 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
Michal Simekd722e862015-12-10 13:33:20 +0100202
Michal Simek9a23c492015-12-10 14:18:15 +0100203 if (mdio_wait(regs))
Michal Simekd722e862015-12-10 13:33:20 +0100204 return 1;
205
206 /* Read data */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100207 *data = __raw_readl(&regs->mdiord);
Michal Simekd722e862015-12-10 13:33:20 +0100208 return 0;
209}
210
Michal Simek9a23c492015-12-10 14:18:15 +0100211static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
Michal Simekd722e862015-12-10 13:33:20 +0100212 u16 data)
213{
Michal Simek9a23c492015-12-10 14:18:15 +0100214 struct emaclite_regs *regs = emaclite->regs;
215
216 if (mdio_wait(regs))
Michal Simekd722e862015-12-10 13:33:20 +0100217 return 1;
218
219 /*
220 * Write the PHY address, register number and clear the OP bit in the
221 * MDIO Address register and then write the value into the MDIO Write
222 * Data register. Finally, set the Status bit in the MDIO Control
223 * register to start a MDIO write transaction.
224 */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100225 u32 ctrl_reg = __raw_readl(&regs->mdioctrl);
226 __raw_writel(~XEL_MDIOADDR_OP_MASK
227 & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
228 | registernum), &regs->mdioaddr);
229 __raw_writel(data, &regs->mdiowr);
230 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, &regs->mdioctrl);
Michal Simekd722e862015-12-10 13:33:20 +0100231
Michal Simek9a23c492015-12-10 14:18:15 +0100232 if (mdio_wait(regs))
Michal Simekd722e862015-12-10 13:33:20 +0100233 return 1;
234
235 return 0;
236}
Michal Simekd722e862015-12-10 13:33:20 +0100237
Michal Simekf03ec012015-12-16 10:40:05 +0100238static void emaclite_stop(struct udevice *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100239{
Michal Simekf03ec012015-12-16 10:40:05 +0100240 debug("eth_stop\n");
Michal Simek89c53892008-03-28 12:41:56 +0100241}
242
Michal Simekd722e862015-12-10 13:33:20 +0100243/* Use MII register 1 (MII status register) to detect PHY */
244#define PHY_DETECT_REG 1
245
246/* Mask used to verify certain PHY features (or register contents)
247 * in the register above:
248 * 0x1000: 10Mbps full duplex support
249 * 0x0800: 10Mbps half duplex support
250 * 0x0008: Auto-negotiation support
251 */
252#define PHY_DETECT_MASK 0x1808
253
Michal Simekd538ee12015-12-10 17:15:52 +0100254static int setup_phy(struct udevice *dev)
Michal Simekd722e862015-12-10 13:33:20 +0100255{
Michal Simek55259e72016-05-18 12:37:22 +0200256 int i, ret;
Michal Simekd722e862015-12-10 13:33:20 +0100257 u16 phyreg;
Michal Simekd538ee12015-12-10 17:15:52 +0100258 struct xemaclite *emaclite = dev_get_priv(dev);
Michal Simekd722e862015-12-10 13:33:20 +0100259 struct phy_device *phydev;
260
261 u32 supported = SUPPORTED_10baseT_Half |
262 SUPPORTED_10baseT_Full |
263 SUPPORTED_100baseT_Half |
264 SUPPORTED_100baseT_Full;
265
266 if (emaclite->phyaddr != -1) {
Michal Simek9a23c492015-12-10 14:18:15 +0100267 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
Michal Simekd722e862015-12-10 13:33:20 +0100268 if ((phyreg != 0xFFFF) &&
269 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
270 /* Found a valid PHY address */
271 debug("Default phy address %d is valid\n",
272 emaclite->phyaddr);
273 } else {
274 debug("PHY address is not setup correctly %d\n",
275 emaclite->phyaddr);
276 emaclite->phyaddr = -1;
277 }
278 }
279
280 if (emaclite->phyaddr == -1) {
281 /* detect the PHY address */
282 for (i = 31; i >= 0; i--) {
Michal Simek9a23c492015-12-10 14:18:15 +0100283 phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
Michal Simekd722e862015-12-10 13:33:20 +0100284 if ((phyreg != 0xFFFF) &&
285 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
286 /* Found a valid PHY address */
287 emaclite->phyaddr = i;
288 debug("emaclite: Found valid phy address, %d\n",
289 i);
290 break;
291 }
292 }
293 }
294
295 /* interface - look at tsec */
296 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
297 PHY_INTERFACE_MODE_MII);
298 /*
299 * Phy can support 1000baseT but device NOT that's why phydev->supported
300 * must be setup for 1000baseT. phydev->advertising setups what speeds
301 * will be used for autonegotiation where 1000baseT must be disabled.
302 */
303 phydev->supported = supported | SUPPORTED_1000baseT_Half |
304 SUPPORTED_1000baseT_Full;
305 phydev->advertising = supported;
306 emaclite->phydev = phydev;
307 phy_config(phydev);
Michal Simek55259e72016-05-18 12:37:22 +0200308 ret = phy_startup(phydev);
309 if (ret)
310 return ret;
Michal Simekd722e862015-12-10 13:33:20 +0100311
312 if (!phydev->link) {
313 printf("%s: No link.\n", phydev->dev->name);
314 return 0;
315 }
316
317 /* Do not setup anything */
318 return 1;
319}
Michal Simekd722e862015-12-10 13:33:20 +0100320
Michal Simekf03ec012015-12-16 10:40:05 +0100321static int emaclite_start(struct udevice *dev)
Michal Simek89c53892008-03-28 12:41:56 +0100322{
Michal Simekd538ee12015-12-10 17:15:52 +0100323 struct xemaclite *emaclite = dev_get_priv(dev);
324 struct eth_pdata *pdata = dev_get_platdata(dev);
Michal Simek9a23c492015-12-10 14:18:15 +0100325 struct emaclite_regs *regs = emaclite->regs;
326
Michal Simek5ac83802011-09-12 21:10:05 +0000327 debug("EmacLite Initialization Started\n");
Michal Simek89c53892008-03-28 12:41:56 +0100328
329/*
330 * TX - TX_PING & TX_PONG initialization
331 */
332 /* Restart PING TX */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100333 __raw_writel(0, &regs->tx_ping_tsr);
Michal Simek89c53892008-03-28 12:41:56 +0100334 /* Copy MAC address */
Michal Simekd538ee12015-12-10 17:15:52 +0100335 xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_ping,
Michal Simeka0b2bfb2015-12-10 15:22:21 +0100336 ENET_ADDR_LENGTH);
Michal Simek89c53892008-03-28 12:41:56 +0100337 /* Set the length */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100338 __raw_writel(ENET_ADDR_LENGTH, &regs->tx_ping_tplr);
Michal Simek89c53892008-03-28 12:41:56 +0100339 /* Update the MAC address in the EMAC Lite */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100340 __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_ping_tsr);
Michal Simek89c53892008-03-28 12:41:56 +0100341 /* Wait for EMAC Lite to finish with the MAC address update */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100342 while ((__raw_readl(&regs->tx_ping_tsr) &
Michal Simek8d95ddb2011-08-25 12:36:39 +0200343 XEL_TSR_PROG_MAC_ADDR) != 0)
344 ;
Michal Simek89c53892008-03-28 12:41:56 +0100345
Michal Simek947324b2011-09-12 21:10:01 +0000346 if (emaclite->txpp) {
347 /* The same operation with PONG TX */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100348 __raw_writel(0, &regs->tx_pong_tsr);
Michal Simekd538ee12015-12-10 17:15:52 +0100349 xemaclite_alignedwrite(pdata->enetaddr, &regs->tx_pong,
Michal Simeka0b2bfb2015-12-10 15:22:21 +0100350 ENET_ADDR_LENGTH);
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100351 __raw_writel(ENET_ADDR_LENGTH, &regs->tx_pong_tplr);
352 __raw_writel(XEL_TSR_PROG_MAC_ADDR, &regs->tx_pong_tsr);
353 while ((__raw_readl(&regs->tx_pong_tsr) &
Michal Simeka0b2bfb2015-12-10 15:22:21 +0100354 XEL_TSR_PROG_MAC_ADDR) != 0)
Michal Simek947324b2011-09-12 21:10:01 +0000355 ;
356 }
Michal Simek89c53892008-03-28 12:41:56 +0100357
358/*
359 * RX - RX_PING & RX_PONG initialization
360 */
361 /* Write out the value to flush the RX buffer */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100362 __raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_ping_rsr);
Michal Simek947324b2011-09-12 21:10:01 +0000363
364 if (emaclite->rxpp)
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100365 __raw_writel(XEL_RSR_RECV_IE_MASK, &regs->rx_pong_rsr);
Michal Simek89c53892008-03-28 12:41:56 +0100366
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100367 __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, &regs->mdioctrl);
368 if (__raw_readl(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
Michal Simekd722e862015-12-10 13:33:20 +0100369 if (!setup_phy(dev))
370 return -1;
Michal Simekd538ee12015-12-10 17:15:52 +0100371
Michal Simek5ac83802011-09-12 21:10:05 +0000372 debug("EmacLite Initialization complete\n");
Michal Simek89c53892008-03-28 12:41:56 +0100373 return 0;
374}
375
Michal Simek26c79452015-12-10 15:42:01 +0100376static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
Michal Simek89c53892008-03-28 12:41:56 +0100377{
Michal Simek26c79452015-12-10 15:42:01 +0100378 u32 tmp;
379 struct emaclite_regs *regs = emaclite->regs;
Michal Simek773cfa82011-08-25 12:47:56 +0200380
Michal Simek89c53892008-03-28 12:41:56 +0100381 /*
382 * Read the other buffer register
383 * and determine if the other buffer is available
384 */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100385 tmp = ~__raw_readl(&regs->tx_ping_tsr);
Michal Simek26c79452015-12-10 15:42:01 +0100386 if (emaclite->txpp)
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100387 tmp |= ~__raw_readl(&regs->tx_pong_tsr);
Michal Simek89c53892008-03-28 12:41:56 +0100388
Michal Simek26c79452015-12-10 15:42:01 +0100389 return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
Michal Simek89c53892008-03-28 12:41:56 +0100390}
391
Michal Simekd538ee12015-12-10 17:15:52 +0100392static int emaclite_send(struct udevice *dev, void *ptr, int len)
Michal Simek042272a2010-10-11 11:41:47 +1000393{
394 u32 reg;
Michal Simekd538ee12015-12-10 17:15:52 +0100395 struct xemaclite *emaclite = dev_get_priv(dev);
Michal Simek5a4baa32015-12-10 15:32:11 +0100396 struct emaclite_regs *regs = emaclite->regs;
Michal Simek89c53892008-03-28 12:41:56 +0100397
Michal Simek042272a2010-10-11 11:41:47 +1000398 u32 maxtry = 1000;
Michal Simek89c53892008-03-28 12:41:56 +0100399
Michal Simek80439252011-09-12 21:10:04 +0000400 if (len > PKTSIZE)
401 len = PKTSIZE;
Michal Simek89c53892008-03-28 12:41:56 +0100402
Michal Simek26c79452015-12-10 15:42:01 +0100403 while (xemaclite_txbufferavailable(emaclite) && maxtry) {
Michal Simek5ac83802011-09-12 21:10:05 +0000404 udelay(10);
Michal Simek89c53892008-03-28 12:41:56 +0100405 maxtry--;
406 }
407
408 if (!maxtry) {
Michal Simek5ac83802011-09-12 21:10:05 +0000409 printf("Error: Timeout waiting for ethernet TX buffer\n");
Michal Simek89c53892008-03-28 12:41:56 +0100410 /* Restart PING TX */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100411 __raw_writel(0, &regs->tx_ping_tsr);
Michal Simek947324b2011-09-12 21:10:01 +0000412 if (emaclite->txpp) {
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100413 __raw_writel(0, &regs->tx_pong_tsr);
Michal Simek947324b2011-09-12 21:10:01 +0000414 }
Michal Simek95efa792011-03-08 04:25:53 +0000415 return -1;
Michal Simek89c53892008-03-28 12:41:56 +0100416 }
417
Michal Simek89c53892008-03-28 12:41:56 +0100418 /* Determine if the expected buffer address is empty */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100419 reg = __raw_readl(&regs->tx_ping_tsr);
Michal Simek15c239c2015-12-10 16:06:07 +0100420 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
Michal Simek00702512015-12-10 16:01:50 +0100421 debug("Send packet from tx_ping buffer\n");
Michal Simek89c53892008-03-28 12:41:56 +0100422 /* Write the frame to the buffer */
Michal Simek00702512015-12-10 16:01:50 +0100423 xemaclite_alignedwrite(ptr, &regs->tx_ping, len);
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100424 __raw_writel(len
425 & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
426 &regs->tx_ping_tplr);
427 reg = __raw_readl(&regs->tx_ping_tsr);
Michal Simek89c53892008-03-28 12:41:56 +0100428 reg |= XEL_TSR_XMIT_BUSY_MASK;
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100429 __raw_writel(reg, &regs->tx_ping_tsr);
Michal Simek95efa792011-03-08 04:25:53 +0000430 return 0;
Michal Simek89c53892008-03-28 12:41:56 +0100431 }
Michal Simek947324b2011-09-12 21:10:01 +0000432
433 if (emaclite->txpp) {
Michal Simek947324b2011-09-12 21:10:01 +0000434 /* Determine if the expected buffer address is empty */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100435 reg = __raw_readl(&regs->tx_pong_tsr);
Michal Simek15c239c2015-12-10 16:06:07 +0100436 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
Michal Simek00702512015-12-10 16:01:50 +0100437 debug("Send packet from tx_pong buffer\n");
Michal Simek947324b2011-09-12 21:10:01 +0000438 /* Write the frame to the buffer */
Michal Simek00702512015-12-10 16:01:50 +0100439 xemaclite_alignedwrite(ptr, &regs->tx_pong, len);
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100440 __raw_writel(len &
Michal Simek00702512015-12-10 16:01:50 +0100441 (XEL_TPLR_LENGTH_MASK_HI |
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100442 XEL_TPLR_LENGTH_MASK_LO),
443 &regs->tx_pong_tplr);
444 reg = __raw_readl(&regs->tx_pong_tsr);
Michal Simek947324b2011-09-12 21:10:01 +0000445 reg |= XEL_TSR_XMIT_BUSY_MASK;
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100446 __raw_writel(reg, &regs->tx_pong_tsr);
Michal Simek947324b2011-09-12 21:10:01 +0000447 return 0;
Michal Simek89c53892008-03-28 12:41:56 +0100448 }
Michal Simek89c53892008-03-28 12:41:56 +0100449 }
Michal Simek947324b2011-09-12 21:10:01 +0000450
Michal Simek5ac83802011-09-12 21:10:05 +0000451 puts("Error while sending frame\n");
Michal Simek95efa792011-03-08 04:25:53 +0000452 return -1;
Michal Simek89c53892008-03-28 12:41:56 +0100453}
454
Michal Simekd538ee12015-12-10 17:15:52 +0100455static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
Michal Simek89c53892008-03-28 12:41:56 +0100456{
Michal Simek4d2749b2015-12-10 16:31:38 +0100457 u32 length, first_read, reg, attempt = 0;
458 void *addr, *ack;
Michal Simek773cfa82011-08-25 12:47:56 +0200459 struct xemaclite *emaclite = dev->priv;
Michal Simek4d2749b2015-12-10 16:31:38 +0100460 struct emaclite_regs *regs = emaclite->regs;
461 struct ethernet_hdr *eth;
462 struct ip_udp_hdr *ip;
Michal Simek89c53892008-03-28 12:41:56 +0100463
Michal Simek4d2749b2015-12-10 16:31:38 +0100464try_again:
465 if (!emaclite->use_rx_pong_buffer_next) {
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100466 reg = __raw_readl(&regs->rx_ping_rsr);
Michal Simek4d2749b2015-12-10 16:31:38 +0100467 debug("Testing data at rx_ping\n");
468 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
469 debug("Data found in rx_ping buffer\n");
470 addr = &regs->rx_ping;
471 ack = &regs->rx_ping_rsr;
Michal Simek947324b2011-09-12 21:10:01 +0000472 } else {
Michal Simek4d2749b2015-12-10 16:31:38 +0100473 debug("Data not found in rx_ping buffer\n");
474 /* Pong buffer is not available - return immediately */
475 if (!emaclite->rxpp)
476 return -1;
477
478 /* Try pong buffer if this is first attempt */
479 if (attempt++)
480 return -1;
481 emaclite->use_rx_pong_buffer_next =
482 !emaclite->use_rx_pong_buffer_next;
483 goto try_again;
484 }
485 } else {
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100486 reg = __raw_readl(&regs->rx_pong_rsr);
Michal Simek4d2749b2015-12-10 16:31:38 +0100487 debug("Testing data at rx_pong\n");
488 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
489 debug("Data found in rx_pong buffer\n");
490 addr = &regs->rx_pong;
491 ack = &regs->rx_pong_rsr;
492 } else {
493 debug("Data not found in rx_pong buffer\n");
494 /* Try ping buffer if this is first attempt */
495 if (attempt++)
496 return -1;
497 emaclite->use_rx_pong_buffer_next =
498 !emaclite->use_rx_pong_buffer_next;
499 goto try_again;
Michal Simek89c53892008-03-28 12:41:56 +0100500 }
Michal Simek89c53892008-03-28 12:41:56 +0100501 }
Michal Simek4d2749b2015-12-10 16:31:38 +0100502
503 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
504 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
505 xemaclite_alignedread(addr, etherrxbuff, first_read);
506
507 /* Detect real packet size */
508 eth = (struct ethernet_hdr *)etherrxbuff;
509 switch (ntohs(eth->et_protlen)) {
510 case PROT_ARP:
511 length = first_read;
512 debug("ARP Packet %x\n", length);
513 break;
514 case PROT_IP:
515 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
516 length = ntohs(ip->ip_len);
517 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
518 debug("IP Packet %x\n", length);
519 break;
520 default:
521 debug("Other Packet\n");
522 length = PKTSIZE;
523 break;
Michal Simek89c53892008-03-28 12:41:56 +0100524 }
525
Michal Simek4d2749b2015-12-10 16:31:38 +0100526 /* Read the rest of the packet which is longer then first read */
527 if (length != first_read)
528 xemaclite_alignedread(addr + first_read,
529 etherrxbuff + first_read,
530 length - first_read);
Michal Simek89c53892008-03-28 12:41:56 +0100531
532 /* Acknowledge the frame */
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100533 reg = __raw_readl(ack);
Michal Simek89c53892008-03-28 12:41:56 +0100534 reg &= ~XEL_RSR_RECV_DONE_MASK;
Zubair Lutfullah Kakakhel611fe0b2016-07-27 12:25:08 +0100535 __raw_writel(reg, ack);
Michal Simek89c53892008-03-28 12:41:56 +0100536
Michal Simek4d2749b2015-12-10 16:31:38 +0100537 debug("Packet receive from 0x%p, length %dB\n", addr, length);
Michal Simekf412b6a2015-12-16 10:52:39 +0100538 *packetp = etherrxbuff;
539 return length;
Michal Simek89c53892008-03-28 12:41:56 +0100540}
Michal Simek042272a2010-10-11 11:41:47 +1000541
Michal Simekd538ee12015-12-10 17:15:52 +0100542static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
543 int devad, int reg)
Michal Simekd722e862015-12-10 13:33:20 +0100544{
545 u32 ret;
Michal Simekd538ee12015-12-10 17:15:52 +0100546 u16 val = 0;
Michal Simekd722e862015-12-10 13:33:20 +0100547
Michal Simekd538ee12015-12-10 17:15:52 +0100548 ret = phyread(bus->priv, addr, reg, &val);
549 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
550 return val;
Michal Simekd722e862015-12-10 13:33:20 +0100551}
552
Michal Simekd538ee12015-12-10 17:15:52 +0100553static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
554 int reg, u16 value)
Michal Simekd722e862015-12-10 13:33:20 +0100555{
Michal Simekd538ee12015-12-10 17:15:52 +0100556 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
557 return phywrite(bus->priv, addr, reg, value);
Michal Simekd722e862015-12-10 13:33:20 +0100558}
Michal Simekd722e862015-12-10 13:33:20 +0100559
Michal Simekd538ee12015-12-10 17:15:52 +0100560static int emaclite_probe(struct udevice *dev)
Michal Simek042272a2010-10-11 11:41:47 +1000561{
Michal Simekd538ee12015-12-10 17:15:52 +0100562 struct xemaclite *emaclite = dev_get_priv(dev);
563 int ret;
Michal Simek042272a2010-10-11 11:41:47 +1000564
Michal Simekd538ee12015-12-10 17:15:52 +0100565 emaclite->bus = mdio_alloc();
566 emaclite->bus->read = emaclite_miiphy_read;
567 emaclite->bus->write = emaclite_miiphy_write;
568 emaclite->bus->priv = emaclite;
Michal Simek042272a2010-10-11 11:41:47 +1000569
Michal Simek6516e3f2016-12-08 10:25:44 +0100570 ret = mdio_register_seq(emaclite->bus, dev->seq);
Michal Simekd538ee12015-12-10 17:15:52 +0100571 if (ret)
572 return ret;
Michal Simek773cfa82011-08-25 12:47:56 +0200573
Michal Simekd538ee12015-12-10 17:15:52 +0100574 return 0;
575}
Michal Simek773cfa82011-08-25 12:47:56 +0200576
Michal Simekd538ee12015-12-10 17:15:52 +0100577static int emaclite_remove(struct udevice *dev)
578{
579 struct xemaclite *emaclite = dev_get_priv(dev);
Michal Simek947324b2011-09-12 21:10:01 +0000580
Michal Simekd538ee12015-12-10 17:15:52 +0100581 free(emaclite->phydev);
582 mdio_unregister(emaclite->bus);
583 mdio_free(emaclite->bus);
Michal Simek042272a2010-10-11 11:41:47 +1000584
Michal Simekd538ee12015-12-10 17:15:52 +0100585 return 0;
586}
Michal Simek042272a2010-10-11 11:41:47 +1000587
Michal Simekd538ee12015-12-10 17:15:52 +0100588static const struct eth_ops emaclite_ops = {
Michal Simekf03ec012015-12-16 10:40:05 +0100589 .start = emaclite_start,
Michal Simekd538ee12015-12-10 17:15:52 +0100590 .send = emaclite_send,
591 .recv = emaclite_recv,
Michal Simekf03ec012015-12-16 10:40:05 +0100592 .stop = emaclite_stop,
Michal Simekd538ee12015-12-10 17:15:52 +0100593};
594
595static int emaclite_ofdata_to_platdata(struct udevice *dev)
596{
597 struct eth_pdata *pdata = dev_get_platdata(dev);
598 struct xemaclite *emaclite = dev_get_priv(dev);
599 int offset = 0;
600
Simon Glassa821c4a2017-05-17 17:18:05 -0600601 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
Zubair Lutfullah Kakakhel39e020e2016-07-27 12:25:07 +0100602 emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
603 0x10000);
Michal Simekd538ee12015-12-10 17:15:52 +0100604
Michal Simekd722e862015-12-10 13:33:20 +0100605 emaclite->phyaddr = -1;
Michal Simekd722e862015-12-10 13:33:20 +0100606
Simon Glasse160f7d2017-01-17 16:52:55 -0700607 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
Michal Simekd538ee12015-12-10 17:15:52 +0100608 "phy-handle");
609 if (offset > 0)
610 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
611 "reg", -1);
Michal Simek042272a2010-10-11 11:41:47 +1000612
Simon Glasse160f7d2017-01-17 16:52:55 -0700613 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Michal Simekd538ee12015-12-10 17:15:52 +0100614 "xlnx,tx-ping-pong", 0);
Simon Glasse160f7d2017-01-17 16:52:55 -0700615 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Michal Simekd538ee12015-12-10 17:15:52 +0100616 "xlnx,rx-ping-pong", 0);
Michal Simekd722e862015-12-10 13:33:20 +0100617
Michal Simekd538ee12015-12-10 17:15:52 +0100618 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
619 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
Michal Simekd722e862015-12-10 13:33:20 +0100620
Michal Simekd538ee12015-12-10 17:15:52 +0100621 return 0;
Michal Simek042272a2010-10-11 11:41:47 +1000622}
Michal Simekd538ee12015-12-10 17:15:52 +0100623
624static const struct udevice_id emaclite_ids[] = {
625 { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
626 { }
627};
628
629U_BOOT_DRIVER(emaclite) = {
630 .name = "emaclite",
631 .id = UCLASS_ETH,
632 .of_match = emaclite_ids,
633 .ofdata_to_platdata = emaclite_ofdata_to_platdata,
634 .probe = emaclite_probe,
635 .remove = emaclite_remove,
636 .ops = &emaclite_ops,
637 .priv_auto_alloc_size = sizeof(struct xemaclite),
638 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
639};