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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ce43893d4dea64cdf5d5f446b8181ef2709eaf09 / . / drivers / clk / renesas / r8a7792-cpg-mssr.c
blob: 260bb892d607c628824f219ff7a1c172fde9f69e [file] [log] [blame]
Marek Vasutce438932018-01-17 23:39:10 +0100[diff] [blame^]1/*
2 * r8a7792 Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2017 Glider bvba
5 *
6 * Based on clk-rcar-gen2.c
7 *
8 * Copyright (C) 2013 Ideas On Board SPRL
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */
14
15#include <common.h>
16#include <clk-uclass.h>
17#include <dm.h>
18
19#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
20
21#include "renesas-cpg-mssr.h"
22#include "rcar-gen2-cpg.h"
23
24enum clk_ids {
25 /* Core Clock Outputs exported to DT */
26 LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
27
28 /* External Input Clocks */
29 CLK_EXTAL,
30
31 /* Internal Core Clocks */
32 CLK_MAIN,
33 CLK_PLL0,
34 CLK_PLL1,
35 CLK_PLL3,
36 CLK_PLL1_DIV2,
37
38 /* Module Clocks */
39 MOD_CLK_BASE
40};
41
42static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
43 /* External Clock Inputs */
44 DEF_INPUT("extal", CLK_EXTAL),
45
46 /* Internal Core Clocks */
47 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
48 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
49 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
50 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
51
52 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
53
54 /* Core Clock Outputs */
55 DEF_BASE("lb", R8A7792_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
56 DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
57
58 DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
59 DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
60 DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
61 DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
62 DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
63 DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
64 DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
65 DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
66 DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
67 DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
68 DEF_FIXED("imp", R8A7792_CLK_IMP, CLK_PLL1, 4, 1),
69 DEF_FIXED("zb3", R8A7792_CLK_ZB3, CLK_PLL3, 4, 1),
70 DEF_FIXED("zb3d2", R8A7792_CLK_ZB3D2, CLK_PLL3, 8, 1),
71 DEF_FIXED("ddr", R8A7792_CLK_DDR, CLK_PLL3, 8, 1),
72 DEF_FIXED("sd", R8A7792_CLK_SD, CLK_PLL1_DIV2, 8, 1),
73 DEF_FIXED("mp", R8A7792_CLK_MP, CLK_PLL1_DIV2, 15, 1),
74 DEF_FIXED("cp", R8A7792_CLK_CP, CLK_PLL1, 48, 1),
75 DEF_FIXED("cpex", R8A7792_CLK_CPEX, CLK_EXTAL, 2, 1),
76 DEF_FIXED("rcan", R8A7792_CLK_RCAN, CLK_PLL1_DIV2, 49, 1),
77 DEF_FIXED("r", R8A7792_CLK_R, CLK_PLL1, 49152, 1),
78 DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
79};
80
81static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
82 DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
83 DEF_MOD("jpu", 106, R8A7792_CLK_M2),
84 DEF_MOD("tmu1", 111, R8A7792_CLK_P),
85 DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
86 DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
87 DEF_MOD("tmu3", 121, R8A7792_CLK_P),
88 DEF_MOD("tmu2", 122, R8A7792_CLK_P),
89 DEF_MOD("cmt0", 124, R8A7792_CLK_R),
90 DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
91 DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
92 DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
93 DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
94 DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
95 DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
96 DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
97 DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
98 DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
99 DEF_MOD("cmt1", 329, R8A7792_CLK_R),
100 DEF_MOD("irqc", 407, R8A7792_CLK_CP),
101 DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
102 DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
103 DEF_MOD("thermal", 522, CLK_EXTAL),
104 DEF_MOD("pwm", 523, R8A7792_CLK_P),
105 DEF_MOD("hscif1", 716, R8A7792_CLK_ZS),
106 DEF_MOD("hscif0", 717, R8A7792_CLK_ZS),
107 DEF_MOD("scif3", 718, R8A7792_CLK_P),
108 DEF_MOD("scif2", 719, R8A7792_CLK_P),
109 DEF_MOD("scif1", 720, R8A7792_CLK_P),
110 DEF_MOD("scif0", 721, R8A7792_CLK_P),
111 DEF_MOD("du1", 723, R8A7792_CLK_ZX),
112 DEF_MOD("du0", 724, R8A7792_CLK_ZX),
113 DEF_MOD("vin5", 804, R8A7792_CLK_ZG),
114 DEF_MOD("vin4", 805, R8A7792_CLK_ZG),
115 DEF_MOD("vin3", 808, R8A7792_CLK_ZG),
116 DEF_MOD("vin2", 809, R8A7792_CLK_ZG),
117 DEF_MOD("vin1", 810, R8A7792_CLK_ZG),
118 DEF_MOD("vin0", 811, R8A7792_CLK_ZG),
119 DEF_MOD("etheravb", 812, R8A7792_CLK_HP),
120 DEF_MOD("imr-lx3", 821, R8A7792_CLK_ZG),
121 DEF_MOD("imr-lsx3-1", 822, R8A7792_CLK_ZG),
122 DEF_MOD("imr-lsx3-0", 823, R8A7792_CLK_ZG),
123 DEF_MOD("imr-lsx3-5", 825, R8A7792_CLK_ZG),
124 DEF_MOD("imr-lsx3-4", 826, R8A7792_CLK_ZG),
125 DEF_MOD("imr-lsx3-3", 827, R8A7792_CLK_ZG),
126 DEF_MOD("imr-lsx3-2", 828, R8A7792_CLK_ZG),
127 DEF_MOD("gyro-adc", 901, R8A7792_CLK_P),
128 DEF_MOD("gpio7", 904, R8A7792_CLK_CP),
129 DEF_MOD("gpio6", 905, R8A7792_CLK_CP),
130 DEF_MOD("gpio5", 907, R8A7792_CLK_CP),
131 DEF_MOD("gpio4", 908, R8A7792_CLK_CP),
132 DEF_MOD("gpio3", 909, R8A7792_CLK_CP),
133 DEF_MOD("gpio2", 910, R8A7792_CLK_CP),
134 DEF_MOD("gpio1", 911, R8A7792_CLK_CP),
135 DEF_MOD("gpio0", 912, R8A7792_CLK_CP),
136 DEF_MOD("gpio11", 913, R8A7792_CLK_CP),
137 DEF_MOD("gpio10", 914, R8A7792_CLK_CP),
138 DEF_MOD("can1", 915, R8A7792_CLK_P),
139 DEF_MOD("can0", 916, R8A7792_CLK_P),
140 DEF_MOD("qspi_mod", 917, R8A7792_CLK_QSPI),
141 DEF_MOD("gpio9", 919, R8A7792_CLK_CP),
142 DEF_MOD("gpio8", 921, R8A7792_CLK_CP),
143 DEF_MOD("i2c5", 925, R8A7792_CLK_HP),
144 DEF_MOD("iicdvfs", 926, R8A7792_CLK_CP),
145 DEF_MOD("i2c4", 927, R8A7792_CLK_HP),
146 DEF_MOD("i2c3", 928, R8A7792_CLK_HP),
147 DEF_MOD("i2c2", 929, R8A7792_CLK_HP),
148 DEF_MOD("i2c1", 930, R8A7792_CLK_HP),
149 DEF_MOD("i2c0", 931, R8A7792_CLK_HP),
150 DEF_MOD("ssi-all", 1005, R8A7792_CLK_P),
151 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
152 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
153};
154
155static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
156 MOD_CLK_ID(408), /* INTC-SYS (GIC) */
157};
158
159/*
160 * CPG Clock Data
161 */
162
163/*
164 * MD EXTAL PLL0 PLL1 PLL3
165 * 14 13 19 (MHz) *1 *2
166 *---------------------------------------------------
167 * 0 0 0 15 x200/3 x208/2 x106
168 * 0 0 1 15 x200/3 x208/2 x88
169 * 0 1 0 20 x150/3 x156/2 x80
170 * 0 1 1 20 x150/3 x156/2 x66
171 * 1 0 0 26 / 2 x230/3 x240/2 x122
172 * 1 0 1 26 / 2 x230/3 x240/2 x102
173 * 1 1 0 30 / 2 x200/3 x208/2 x106
174 * 1 1 1 30 / 2 x200/3 x208/2 x88
175 *
176 * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
177 * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
178 */
179#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
180 (((md) & BIT(13)) >> 12) | \
181 (((md) & BIT(19)) >> 19))
182static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
183 { 1, 208, 106, 200 },
184 { 1, 208, 88, 200 },
185 { 1, 156, 80, 150 },
186 { 1, 156, 66, 150 },
187 { 2, 240, 122, 230 },
188 { 2, 240, 102, 230 },
189 { 2, 208, 106, 200 },
190 { 2, 208, 88, 200 },
191};
192
193static const struct mstp_stop_table r8a7792_mstp_table[] = {
194 { 0x00400801, 0x400000, 0x00400801, 0x0 },
195 { 0x9B6F987F, 0x0, 0x9B6F987F, 0x0 },
196 { 0x108CE100, 0x0, 0x108CE100, 0x80000 },
197 { 0x20004010, 0x4000, 0x20004010, 0x0 },
198 { 0x80000184, 0x180, 0x80000184, 0x0 },
199 { 0x44C00004, 0x0, 0x44C00004, 0x0 },
200 { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
201 { 0x01BF0000, 0x200000, 0x01BF0000, 0x0 },
202 { 0x1FE01FB0, 0x0, 0x1FE01FB0, 0x0 },
203 { 0xFE2BFFB2, 0x20000, 0xFE2BFFB2, 0x0 },
204 { 0x00001820, 0x0, 0x00001820, 0x0 },
205 { 0x00000008, 0x0, 0x00000008, 0x0 },
206};
207
208static const void *r8a7792_get_pll_config(const u32 cpg_mode)
209{
210 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
211}
212
213static const struct cpg_mssr_info r8a7792_cpg_mssr_info = {
214 .core_clk = r8a7792_core_clks,
215 .core_clk_size = ARRAY_SIZE(r8a7792_core_clks),
216 .mod_clk = r8a7792_mod_clks,
217 .mod_clk_size = ARRAY_SIZE(r8a7792_mod_clks),
218 .mstp_table = r8a7792_mstp_table,
219 .mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table),
220 .reset_node = "renesas,r8a7792-rst",
221 .extal_usb_node = "usb_extal",
222 .mod_clk_base = MOD_CLK_BASE,
223 .clk_extal_id = CLK_EXTAL,
224 .clk_extal_usb_id = CLK_USB_EXTAL,
225 .pll0_div = 2,
226 .get_pll_config = r8a7792_get_pll_config,
227};
228
229static const struct udevice_id r8a7792_clk_ids[] = {
230 {
231 .compatible = "renesas,r8a7792-cpg-mssr",
232 .data = (ulong)&r8a7792_cpg_mssr_info
233 },
234 {
235 .compatible = "renesas,r8a7793-cpg-mssr",
236 .data = (ulong)&r8a7792_cpg_mssr_info
237 },
238 { }
239};
240
241U_BOOT_DRIVER(clk_r8a7792) = {
242 .name = "clk_r8a7792",
243 .id = UCLASS_CLK,
244 .of_match = r8a7792_clk_ids,
245 .priv_auto_alloc_size = sizeof(struct gen2_clk_priv),
246 .ops = &gen2_clk_ops,
247 .probe = gen2_clk_probe,
248 .remove = gen2_clk_remove,
249};