blob: 96cf5fece75f849cfa03bb04f0f06e850e708f76 [file] [log] [blame]
Peng Fanf77d4412018-10-18 14:28:30 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright 2018 NXP
4 * Peng Fan <peng.fan@nxp.com>
5 */
6
Peng Fanf77d4412018-10-18 14:28:30 +02007#include <clk-uclass.h>
8#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -070010#include <malloc.h>
Peng Fan99ac6c72023-04-28 12:08:09 +080011#include <firmware/imx/sci/sci.h>
Peng Fanf77d4412018-10-18 14:28:30 +020012#include <asm/arch/clock.h>
13#include <dt-bindings/clock/imx8qxp-clock.h>
14#include <dt-bindings/soc/imx_rsrc.h>
15#include <misc.h>
16
Peng Fan98c63a72019-03-05 02:32:33 +000017#include "clk-imx8.h"
Peng Fanf77d4412018-10-18 14:28:30 +020018
Peng Fan98c63a72019-03-05 02:32:33 +000019__weak ulong imx8_clk_get_rate(struct clk *clk)
Peng Fanf77d4412018-10-18 14:28:30 +020020{
Peng Fanf77d4412018-10-18 14:28:30 +020021 return 0;
22}
23
Peng Fan98c63a72019-03-05 02:32:33 +000024__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
25{
26 return 0;
27}
28
29__weak int __imx8_clk_enable(struct clk *clk, bool enable)
30{
Simon Glass9042bf62021-03-25 10:26:08 +130031 return -EINVAL;
Peng Fan98c63a72019-03-05 02:32:33 +000032}
33
Peng Fanf77d4412018-10-18 14:28:30 +020034static int imx8_clk_disable(struct clk *clk)
35{
36 return __imx8_clk_enable(clk, 0);
37}
38
39static int imx8_clk_enable(struct clk *clk)
40{
41 return __imx8_clk_enable(clk, 1);
42}
43
Simon Glass8dd86202023-02-05 15:36:26 -070044#if IS_ENABLED(CONFIG_CMD_CLK)
Igor Prusovbc3e3132023-11-09 13:55:15 +030045static void imx8_clk_dump(struct udevice *dev)
Peng Fanf77d4412018-10-18 14:28:30 +020046{
Peng Fanf77d4412018-10-18 14:28:30 +020047 struct clk clk;
48 unsigned long rate;
49 int i, ret;
50
Peng Fanf77d4412018-10-18 14:28:30 +020051 printf("Clk\t\tHz\n");
52
Peng Fan98c63a72019-03-05 02:32:33 +000053 for (i = 0; i < num_clks; i++) {
Peng Fanf77d4412018-10-18 14:28:30 +020054 clk.id = imx8_clk_names[i].id;
55 ret = clk_request(dev, &clk);
56 if (ret < 0) {
57 debug("%s clk_request() failed: %d\n", __func__, ret);
58 continue;
59 }
60
61 ret = clk_get_rate(&clk);
62 rate = ret;
63
Simon Glass9042bf62021-03-25 10:26:08 +130064 if (ret == -EINVAL) {
Peng Fanf77d4412018-10-18 14:28:30 +020065 printf("clk ID %lu not supported yet\n",
66 imx8_clk_names[i].id);
67 continue;
68 }
69 if (ret < 0) {
70 printf("%s %lu: get_rate err: %d\n",
71 __func__, imx8_clk_names[i].id, ret);
72 continue;
73 }
74
75 printf("%s(%3lu):\t%lu\n",
76 imx8_clk_names[i].name, imx8_clk_names[i].id, rate);
77 }
Peng Fanf77d4412018-10-18 14:28:30 +020078}
79#endif
80
81static struct clk_ops imx8_clk_ops = {
82 .set_rate = imx8_clk_set_rate,
83 .get_rate = imx8_clk_get_rate,
84 .enable = imx8_clk_enable,
85 .disable = imx8_clk_disable,
Igor Prusovbc3e3132023-11-09 13:55:15 +030086#if IS_ENABLED(CONFIG_CMD_CLK)
87 .dump = imx8_clk_dump,
88#endif
Peng Fanf77d4412018-10-18 14:28:30 +020089};
90
91static int imx8_clk_probe(struct udevice *dev)
92{
93 return 0;
94}
95
96static const struct udevice_id imx8_clk_ids[] = {
97 { .compatible = "fsl,imx8qxp-clk" },
Peng Fane45efe92019-03-05 02:32:35 +000098 { .compatible = "fsl,imx8qm-clk" },
Peng Fanf77d4412018-10-18 14:28:30 +020099 { },
100};
101
102U_BOOT_DRIVER(imx8_clk) = {
103 .name = "clk_imx8",
104 .id = UCLASS_CLK,
105 .of_match = imx8_clk_ids,
106 .ops = &imx8_clk_ops,
107 .probe = imx8_clk_probe,
108 .flags = DM_FLAG_PRE_RELOC,
109};