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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / ce7005620626cbbba4ec933e1432c28c4ffa353a / . / dts / upstream / Bindings / ufs / qcom,ufs.yaml
blob: 25a5edeea164592944cb9ce36b1559cd3cf52e87 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Universal Flash Storage (UFS) Controller
8
9maintainers:
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
12
13# Select only our matches, not all jedec,ufs-2.0
14select:
15 properties:
16 compatible:
17 contains:
18 const: qcom,ufshc
19 required:
20 - compatible
21
22properties:
23 compatible:
24 items:
25 - enum:
26 - qcom,msm8994-ufshc
27 - qcom,msm8996-ufshc
28 - qcom,msm8998-ufshc
29 - qcom,sa8775p-ufshc
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]30 - qcom,sc7180-ufshc
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]31 - qcom,sc7280-ufshc
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]32 - qcom,sc8180x-ufshc
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]33 - qcom,sc8280xp-ufshc
34 - qcom,sdm845-ufshc
35 - qcom,sm6115-ufshc
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]36 - qcom,sm6125-ufshc
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]37 - qcom,sm6350-ufshc
38 - qcom,sm8150-ufshc
39 - qcom,sm8250-ufshc
40 - qcom,sm8350-ufshc
41 - qcom,sm8450-ufshc
42 - qcom,sm8550-ufshc
43 - qcom,sm8650-ufshc
44 - const: qcom,ufshc
45 - const: jedec,ufs-2.0
46
47 clocks:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]48 minItems: 7
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]49 maxItems: 9
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]50
51 clock-names:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]52 minItems: 7
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]53 maxItems: 9
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]54
55 dma-coherent: true
56
57 interconnects:
58 minItems: 2
59 maxItems: 2
60
61 interconnect-names:
62 items:
63 - const: ufs-ddr
64 - const: cpu-ufs
65
66 iommus:
67 minItems: 1
68 maxItems: 2
69
70 phys:
71 maxItems: 1
72
73 phy-names:
74 items:
75 - const: ufsphy
76
77 power-domains:
78 maxItems: 1
79
80 qcom,ice:
81 $ref: /schemas/types.yaml#/definitions/phandle
82 description: phandle to the Inline Crypto Engine node
83
84 reg:
85 minItems: 1
86 maxItems: 2
87
88 reg-names:
89 items:
90 - const: std
91 - const: ice
92
93 required-opps:
94 maxItems: 1
95
96 resets:
97 maxItems: 1
98
99 '#reset-cells':
100 const: 1
101
102 reset-names:
103 items:
104 - const: rst
105
106 reset-gpios:
107 maxItems: 1
108 description:
109 GPIO connected to the RESET pin of the UFS memory device.
110
111required:
112 - compatible
113 - reg
114
115allOf:
116 - $ref: ufs-common.yaml
117
118 - if:
119 properties:
120 compatible:
121 contains:
122 enum:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]123 - qcom,sc7180-ufshc
124 then:
125 properties:
126 clocks:
127 minItems: 7
128 maxItems: 7
129 clock-names:
130 items:
131 - const: core_clk
132 - const: bus_aggr_clk
133 - const: iface_clk
134 - const: core_clk_unipro
135 - const: ref_clk
136 - const: tx_lane0_sync_clk
137 - const: rx_lane0_sync_clk
138 reg:
139 maxItems: 1
140 reg-names:
141 maxItems: 1
142
143 - if:
144 properties:
145 compatible:
146 contains:
147 enum:
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]148 - qcom,msm8998-ufshc
149 - qcom,sa8775p-ufshc
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]150 - qcom,sc7280-ufshc
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]151 - qcom,sc8180x-ufshc
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]152 - qcom,sc8280xp-ufshc
153 - qcom,sm8250-ufshc
154 - qcom,sm8350-ufshc
155 - qcom,sm8450-ufshc
156 - qcom,sm8550-ufshc
157 - qcom,sm8650-ufshc
158 then:
159 properties:
160 clocks:
161 minItems: 8
162 maxItems: 8
163 clock-names:
164 items:
165 - const: core_clk
166 - const: bus_aggr_clk
167 - const: iface_clk
168 - const: core_clk_unipro
169 - const: ref_clk
170 - const: tx_lane0_sync_clk
171 - const: rx_lane0_sync_clk
172 - const: rx_lane1_sync_clk
173 reg:
174 minItems: 1
175 maxItems: 1
176 reg-names:
177 maxItems: 1
178
179 - if:
180 properties:
181 compatible:
182 contains:
183 enum:
184 - qcom,sdm845-ufshc
185 - qcom,sm6350-ufshc
186 - qcom,sm8150-ufshc
187 then:
188 properties:
189 clocks:
190 minItems: 9
191 maxItems: 9
192 clock-names:
193 items:
194 - const: core_clk
195 - const: bus_aggr_clk
196 - const: iface_clk
197 - const: core_clk_unipro
198 - const: ref_clk
199 - const: tx_lane0_sync_clk
200 - const: rx_lane0_sync_clk
201 - const: rx_lane1_sync_clk
202 - const: ice_core_clk
203 reg:
204 minItems: 2
205 maxItems: 2
206 reg-names:
207 minItems: 2
208 required:
209 - reg-names
210
211 - if:
212 properties:
213 compatible:
214 contains:
215 enum:
216 - qcom,msm8996-ufshc
217 then:
218 properties:
219 clocks:
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]220 minItems: 9
221 maxItems: 9
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]222 clock-names:
223 items:
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]224 - const: core_clk
225 - const: bus_clk
226 - const: bus_aggr_clk
227 - const: iface_clk
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]228 - const: core_clk_unipro
229 - const: core_clk_ice
230 - const: ref_clk
231 - const: tx_lane0_sync_clk
232 - const: rx_lane0_sync_clk
233 reg:
234 minItems: 1
235 maxItems: 1
236 reg-names:
237 maxItems: 1
238
239 - if:
240 properties:
241 compatible:
242 contains:
243 enum:
244 - qcom,sm6115-ufshc
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]245 - qcom,sm6125-ufshc
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]246 then:
247 properties:
248 clocks:
249 minItems: 8
250 maxItems: 8
251 clock-names:
252 items:
253 - const: core_clk
254 - const: bus_aggr_clk
255 - const: iface_clk
256 - const: core_clk_unipro
257 - const: ref_clk
258 - const: tx_lane0_sync_clk
259 - const: rx_lane0_sync_clk
260 - const: ice_core_clk
261 reg:
262 minItems: 2
263 maxItems: 2
264 reg-names:
265 minItems: 2
266 required:
267 - reg-names
268
269 # TODO: define clock bindings for qcom,msm8994-ufshc
270
271 - if:
272 required:
273 - qcom,ice
274 then:
275 properties:
276 reg:
277 maxItems: 1
278 clocks:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]279 minItems: 7
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]280 maxItems: 8
281 else:
282 properties:
283 reg:
284 minItems: 1
285 maxItems: 2
286 clocks:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]287 minItems: 7
Tom Rini6b642ac2024-10-01 12:20:28 -0600[diff] [blame]288 maxItems: 9
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]289
290unevaluatedProperties: false
291
292examples:
293 - |
294 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
295 #include <dt-bindings/clock/qcom,rpmh.h>
296 #include <dt-bindings/gpio/gpio.h>
297 #include <dt-bindings/interconnect/qcom,sm8450.h>
298 #include <dt-bindings/interrupt-controller/arm-gic.h>
299
300 soc {
301 #address-cells = <2>;
302 #size-cells = <2>;
303
304 ufs@1d84000 {
305 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
306 "jedec,ufs-2.0";
307 reg = <0 0x01d84000 0 0x3000>;
308 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
309 phys = <&ufs_mem_phy_lanes>;
310 phy-names = "ufsphy";
311 lanes-per-direction = <2>;
312 #reset-cells = <1>;
313 resets = <&gcc GCC_UFS_PHY_BCR>;
314 reset-names = "rst";
315 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
316
317 vcc-supply = <&vreg_l7b_2p5>;
318 vcc-max-microamp = <1100000>;
319 vccq-supply = <&vreg_l9b_1p2>;
320 vccq-max-microamp = <1200000>;
321
322 power-domains = <&gcc UFS_PHY_GDSC>;
323 iommus = <&apps_smmu 0xe0 0x0>;
324 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
325 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
326 interconnect-names = "ufs-ddr", "cpu-ufs";
327
328 clock-names = "core_clk",
329 "bus_aggr_clk",
330 "iface_clk",
331 "core_clk_unipro",
332 "ref_clk",
333 "tx_lane0_sync_clk",
334 "rx_lane0_sync_clk",
335 "rx_lane1_sync_clk";
336 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
337 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
338 <&gcc GCC_UFS_PHY_AHB_CLK>,
339 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
340 <&rpmhcc RPMH_CXO_CLK>,
341 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
342 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
343 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
344 freq-table-hz = <75000000 300000000>,
345 <0 0>,
346 <0 0>,
347 <75000000 300000000>,
348 <75000000 300000000>,
349 <0 0>,
350 <0 0>,
351 <0 0>;
352 qcom,ice = <&ice>;
353 };
354 };