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wdenkd126bfb2003-04-10 11:18:18 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkd126bfb2003-04-10 11:18:18 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkd126bfb2003-04-10 11:18:18 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC860 1
21#define CONFIG_MPC860T 1
22#define CONFIG_MPC862 1
Wolfgang Denk23c5d252014-10-24 15:31:26 +020023#define CONFIG_DISPLAY_BOARDINFO
wdenkd126bfb2003-04-10 11:18:18 +000024
25#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
26
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027#define CONFIG_SYS_TEXT_BASE 0x40000000
28
wdenkd126bfb2003-04-10 11:18:18 +000029#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020030#define CONFIG_SYS_SMC_RXBUFLEN 128
31#define CONFIG_SYS_MAXIDLE 10
wdenkd126bfb2003-04-10 11:18:18 +000032#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
33
wdenkae3af052003-08-07 22:18:11 +000034#define CONFIG_BOOTCOUNT_LIMIT
wdenkd126bfb2003-04-10 11:18:18 +000035
wdenkae3af052003-08-07 22:18:11 +000036#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkd126bfb2003-04-10 11:18:18 +000037
38#define CONFIG_BOARD_TYPES 1 /* support board types */
39
40#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010041 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenkd126bfb2003-04-10 11:18:18 +000042 "echo"
43
44#undef CONFIG_BOOTARGS
45
46#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000047 "netdev=eth0\0" \
wdenkd126bfb2003-04-10 11:18:18 +000048 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010049 "nfsroot=${serverip}:${rootpath}\0" \
wdenkd126bfb2003-04-10 11:18:18 +000050 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010051 "addip=setenv bootargs ${bootargs} " \
52 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
53 ":${hostname}:${netdev}:off panic=1\0" \
wdenkd126bfb2003-04-10 11:18:18 +000054 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010055 "bootm ${kernel_addr}\0" \
wdenkd126bfb2003-04-10 11:18:18 +000056 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010057 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
58 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkd126bfb2003-04-10 11:18:18 +000059 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020060 "hostname=TQM862L\0" \
61 "bootfile=TQM862L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020062 "fdt_addr=40040000\0" \
63 "kernel_addr=40060000\0" \
64 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020065 "u-boot=TQM862L/u-image.bin\0" \
66 "load=tftp 200000 ${u-boot}\0" \
67 "update=prot off 40000000 +${filesize};" \
68 "era 40000000 +${filesize};" \
69 "cp.b 200000 40000000 ${filesize};" \
70 "sete filesize;save\0" \
wdenkd126bfb2003-04-10 11:18:18 +000071 ""
72#define CONFIG_BOOTCOMMAND "run flash_self"
73
74#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkd126bfb2003-04-10 11:18:18 +000076
77#undef CONFIG_WATCHDOG /* watchdog disabled */
78
79#define CONFIG_STATUS_LED 1 /* Status LED enabled */
80
81#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
82
Jon Loeliger37d4bb72007-07-09 21:38:02 -050083/*
84 * BOOTP options
85 */
86#define CONFIG_BOOTP_SUBNETMASK
87#define CONFIG_BOOTP_GATEWAY
88#define CONFIG_BOOTP_HOSTNAME
89#define CONFIG_BOOTP_BOOTPATH
90#define CONFIG_BOOTP_BOOTFILESIZE
91
wdenkd126bfb2003-04-10 11:18:18 +000092#define CONFIG_MAC_PARTITION
93#define CONFIG_DOS_PARTITION
94
95#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
96
Jon Loeliger26946902007-07-04 22:30:50 -050097/*
98 * Command line configuration.
99 */
Jon Loeliger26946902007-07-04 22:30:50 -0500100#define CONFIG_CMD_DATE
Jon Loeliger26946902007-07-04 22:30:50 -0500101#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200102#define CONFIG_CMD_JFFS2
wdenkd126bfb2003-04-10 11:18:18 +0000103
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200104#define CONFIG_NETCONSOLE
105
wdenkd126bfb2003-04-10 11:18:18 +0000106/*
107 * Miscellaneous configurable options
108 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkd126bfb2003-04-10 11:18:18 +0000110
Wolfgang Denk2751a952006-10-28 02:29:14 +0200111#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
wdenkd126bfb2003-04-10 11:18:18 +0000112
Jon Loeliger26946902007-07-04 22:30:50 -0500113#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkd126bfb2003-04-10 11:18:18 +0000115#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkd126bfb2003-04-10 11:18:18 +0000117#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
119#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
120#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkd126bfb2003-04-10 11:18:18 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
123#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkd126bfb2003-04-10 11:18:18 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkd126bfb2003-04-10 11:18:18 +0000126
wdenkd126bfb2003-04-10 11:18:18 +0000127/*
128 * Low Level Configuration Settings
129 * (address mappings, register initial values, etc.)
130 * You should know what you are doing if you make changes here.
131 */
132/*-----------------------------------------------------------------------
133 * Internal Memory Mapped Register
134 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_IMMR 0xFFF00000
wdenkd126bfb2003-04-10 11:18:18 +0000136
137/*-----------------------------------------------------------------------
138 * Definitions for initial stack pointer and data area (in DPRAM)
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200141#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200142#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkd126bfb2003-04-10 11:18:18 +0000144
145/*-----------------------------------------------------------------------
146 * Start addresses for the final memory configuration
147 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkd126bfb2003-04-10 11:18:18 +0000149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_SDRAM_BASE 0x00000000
151#define CONFIG_SYS_FLASH_BASE 0x40000000
152#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
153#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
154#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkd126bfb2003-04-10 11:18:18 +0000155
156/*
157 * For booting Linux, the board info and command line data
158 * have to be in the first 8 MB of memory, since this is
159 * the maximum mapped by the Linux kernel during initialization.
160 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkd126bfb2003-04-10 11:18:18 +0000162
163/*-----------------------------------------------------------------------
164 * FLASH organization
165 */
wdenkd126bfb2003-04-10 11:18:18 +0000166
Martin Krausee318d9e2007-09-27 11:10:08 +0200167/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200169#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
171#define CONFIG_SYS_FLASH_EMPTY_INFO
172#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
173#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
174#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkd126bfb2003-04-10 11:18:18 +0000175
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200176#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200177#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
178#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkd126bfb2003-04-10 11:18:18 +0000179
180/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200181#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
182#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkd126bfb2003-04-10 11:18:18 +0000183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200185
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200186#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
187
wdenkd126bfb2003-04-10 11:18:18 +0000188/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200189 * Dynamic MTD partition support
190 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100191#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200192#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
193#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200194#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
195
196#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
197 "128k(dtb)," \
198 "1664k(kernel)," \
199 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200200 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200201
202/*-----------------------------------------------------------------------
wdenkd126bfb2003-04-10 11:18:18 +0000203 * Hardware Information Block
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
206#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
207#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkd126bfb2003-04-10 11:18:18 +0000208
209/*-----------------------------------------------------------------------
210 * Cache Configuration
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500213#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkd126bfb2003-04-10 11:18:18 +0000215#endif
216
217/*-----------------------------------------------------------------------
218 * SYPCR - System Protection Control 11-9
219 * SYPCR can only be written once after reset!
220 *-----------------------------------------------------------------------
221 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
222 */
223#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkd126bfb2003-04-10 11:18:18 +0000225 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
226#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkd126bfb2003-04-10 11:18:18 +0000228#endif
229
230/*-----------------------------------------------------------------------
231 * SIUMCR - SIU Module Configuration 11-6
232 *-----------------------------------------------------------------------
233 * PCMCIA config., multi-function pin tri-state
234 */
235#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd126bfb2003-04-10 11:18:18 +0000237#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkd126bfb2003-04-10 11:18:18 +0000239#endif /* CONFIG_CAN_DRIVER */
240
241/*-----------------------------------------------------------------------
242 * TBSCR - Time Base Status and Control 11-26
243 *-----------------------------------------------------------------------
244 * Clear Reference Interrupt Status, Timebase freezing enabled
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkd126bfb2003-04-10 11:18:18 +0000247
248/*-----------------------------------------------------------------------
249 * RTCSC - Real-Time Clock Status and Control Register 11-27
250 *-----------------------------------------------------------------------
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkd126bfb2003-04-10 11:18:18 +0000253
254/*-----------------------------------------------------------------------
255 * PISCR - Periodic Interrupt Status and Control 11-31
256 *-----------------------------------------------------------------------
257 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkd126bfb2003-04-10 11:18:18 +0000260
261/*-----------------------------------------------------------------------
262 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
263 *-----------------------------------------------------------------------
264 * Reset PLL lock status sticky bit, timer expired status bit and timer
265 * interrupt status bit
wdenkd126bfb2003-04-10 11:18:18 +0000266 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkd126bfb2003-04-10 11:18:18 +0000268
269/*-----------------------------------------------------------------------
270 * SCCR - System Clock and reset Control Register 15-27
271 *-----------------------------------------------------------------------
272 * Set clock output, timebase and RTC source and divider,
273 * power management and some other internal clocks
274 */
275#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkd126bfb2003-04-10 11:18:18 +0000277 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
278 SCCR_DFALCD00)
wdenkd126bfb2003-04-10 11:18:18 +0000279
280/*-----------------------------------------------------------------------
281 * PCMCIA stuff
282 *-----------------------------------------------------------------------
283 *
284 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
286#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
287#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
288#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
289#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
290#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
291#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
292#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkd126bfb2003-04-10 11:18:18 +0000293
294/*-----------------------------------------------------------------------
295 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
296 *-----------------------------------------------------------------------
297 */
298
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000299#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkd126bfb2003-04-10 11:18:18 +0000300#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
301
302#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
303#undef CONFIG_IDE_LED /* LED for ide not supported */
304#undef CONFIG_IDE_RESET /* reset for ide not supported */
305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
307#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkd126bfb2003-04-10 11:18:18 +0000308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkd126bfb2003-04-10 11:18:18 +0000310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkd126bfb2003-04-10 11:18:18 +0000312
313/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd126bfb2003-04-10 11:18:18 +0000315
316/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkd126bfb2003-04-10 11:18:18 +0000318
319/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkd126bfb2003-04-10 11:18:18 +0000321
322/*-----------------------------------------------------------------------
323 *
324 *-----------------------------------------------------------------------
325 *
326 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_DER 0
wdenkd126bfb2003-04-10 11:18:18 +0000328
329/*
330 * Init Memory Controller:
331 *
332 * BR0/1 and OR0/1 (FLASH)
333 */
334
335#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
wdenk71f95112003-06-15 22:40:42 +0000336#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
wdenkd126bfb2003-04-10 11:18:18 +0000337
338/* used to re-map FLASH both when starting from SRAM or FLASH:
339 * restrict access enough to keep SRAM working (if any)
340 * but not too much to meddle with FLASH accesses
341 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
343#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkd126bfb2003-04-10 11:18:18 +0000344
345/*
346 * FLASH timing:
347 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkd126bfb2003-04-10 11:18:18 +0000349 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkd126bfb2003-04-10 11:18:18 +0000350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
352#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
353#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkd126bfb2003-04-10 11:18:18 +0000354
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
356#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
357#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkd126bfb2003-04-10 11:18:18 +0000358
359/*
360 * BR2/3 and OR2/3 (SDRAM)
361 *
362 */
363#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
364#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
365#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
366
367/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkd126bfb2003-04-10 11:18:18 +0000369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
371#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd126bfb2003-04-10 11:18:18 +0000372
373#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
375#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkd126bfb2003-04-10 11:18:18 +0000376#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
378#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
379#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
380#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkd126bfb2003-04-10 11:18:18 +0000381 BR_PS_8 | BR_MS_UPMB | BR_V )
382#endif /* CONFIG_CAN_DRIVER */
383
384/*
385 * Memory Periodic Timer Prescaler
386 *
387 * The Divider for PTA (refresh timer) configuration is based on an
388 * example SDRAM configuration (64 MBit, one bank). The adjustment to
389 * the number of chip selects (NCS) and the actually needed refresh
390 * rate is done by setting MPTPR.
391 *
392 * PTA is calculated from
393 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
394 *
395 * gclk CPU clock (not bus clock!)
396 * Trefresh Refresh cycle * 4 (four word bursts used)
397 *
398 * 4096 Rows from SDRAM example configuration
399 * 1000 factor s -> ms
400 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
401 * 4 Number of refresh cycles per period
402 * 64 Refresh cycle in ms per number of rows
403 * --------------------------------------------
404 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
405 *
wdenk73a8b272003-06-05 19:27:42 +0000406 * 50 MHz => 50.000.000 / Divider = 98
407 * 66 Mhz => 66.000.000 / Divider = 129
408 * 80 Mhz => 80.000.000 / Divider = 156
409 * 100 Mhz => 100.000.000 / Divider = 195
wdenkd126bfb2003-04-10 11:18:18 +0000410 */
wdenke9132ea2004-04-24 23:23:30 +0000411
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
413#define CONFIG_SYS_MAMR_PTA 98
wdenkd126bfb2003-04-10 11:18:18 +0000414
415/*
416 * For 16 MBit, refresh rates could be 31.3 us
417 * (= 64 ms / 2K = 125 / quad bursts).
418 * For a simpler initialization, 15.6 us is used instead.
419 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
421 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkd126bfb2003-04-10 11:18:18 +0000422 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
424#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkd126bfb2003-04-10 11:18:18 +0000425
426/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
428#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkd126bfb2003-04-10 11:18:18 +0000429
430/*
431 * MAMR settings for SDRAM
432 */
433
434/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd126bfb2003-04-10 11:18:18 +0000436 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
437 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
438/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkd126bfb2003-04-10 11:18:18 +0000440 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
441 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
442
wdenkd126bfb2003-04-10 11:18:18 +0000443#define CONFIG_SCC1_ENET
444#define CONFIG_FEC_ENET
Heiko Schocher48690d82010-07-20 17:45:02 +0200445#define CONFIG_ETHPRIME "SCC"
wdenkd126bfb2003-04-10 11:18:18 +0000446
Heiko Schocher7026ead2010-02-09 15:50:27 +0100447#define CONFIG_HWCONFIG 1
448
wdenkd126bfb2003-04-10 11:18:18 +0000449#endif /* __CONFIG_H */