Chin Liang See | 3eb3e72 | 2014-09-12 00:42:17 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013-2014 Altera Corporation <www.altera.com> |
| 3 | * Copyright (C) 2009-2010, Intel Corporation and its suppliers. |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
Scott Wood | d396372 | 2015-06-26 19:03:26 -0500 | [diff] [blame] | 8 | #ifndef __DENALI_H__ |
| 9 | #define __DENALI_H__ |
| 10 | |
Chin Liang See | 3eb3e72 | 2014-09-12 00:42:17 -0500 | [diff] [blame] | 11 | #include <linux/mtd/nand.h> |
| 12 | |
| 13 | #define DEVICE_RESET 0x0 |
| 14 | #define DEVICE_RESET__BANK0 0x0001 |
| 15 | #define DEVICE_RESET__BANK1 0x0002 |
| 16 | #define DEVICE_RESET__BANK2 0x0004 |
| 17 | #define DEVICE_RESET__BANK3 0x0008 |
| 18 | |
| 19 | #define TRANSFER_SPARE_REG 0x10 |
| 20 | #define TRANSFER_SPARE_REG__FLAG 0x0001 |
| 21 | |
| 22 | #define LOAD_WAIT_CNT 0x20 |
| 23 | #define LOAD_WAIT_CNT__VALUE 0xffff |
| 24 | |
| 25 | #define PROGRAM_WAIT_CNT 0x30 |
| 26 | #define PROGRAM_WAIT_CNT__VALUE 0xffff |
| 27 | |
| 28 | #define ERASE_WAIT_CNT 0x40 |
| 29 | #define ERASE_WAIT_CNT__VALUE 0xffff |
| 30 | |
| 31 | #define INT_MON_CYCCNT 0x50 |
| 32 | #define INT_MON_CYCCNT__VALUE 0xffff |
| 33 | |
| 34 | #define RB_PIN_ENABLED 0x60 |
| 35 | #define RB_PIN_ENABLED__BANK0 0x0001 |
| 36 | #define RB_PIN_ENABLED__BANK1 0x0002 |
| 37 | #define RB_PIN_ENABLED__BANK2 0x0004 |
| 38 | #define RB_PIN_ENABLED__BANK3 0x0008 |
| 39 | |
| 40 | #define MULTIPLANE_OPERATION 0x70 |
| 41 | #define MULTIPLANE_OPERATION__FLAG 0x0001 |
| 42 | |
| 43 | #define MULTIPLANE_READ_ENABLE 0x80 |
| 44 | #define MULTIPLANE_READ_ENABLE__FLAG 0x0001 |
| 45 | |
| 46 | #define COPYBACK_DISABLE 0x90 |
| 47 | #define COPYBACK_DISABLE__FLAG 0x0001 |
| 48 | |
| 49 | #define CACHE_WRITE_ENABLE 0xa0 |
| 50 | #define CACHE_WRITE_ENABLE__FLAG 0x0001 |
| 51 | |
| 52 | #define CACHE_READ_ENABLE 0xb0 |
| 53 | #define CACHE_READ_ENABLE__FLAG 0x0001 |
| 54 | |
| 55 | #define PREFETCH_MODE 0xc0 |
| 56 | #define PREFETCH_MODE__PREFETCH_EN 0x0001 |
| 57 | #define PREFETCH_MODE__PREFETCH_BURST_LENGTH 0xfff0 |
| 58 | |
| 59 | #define CHIP_ENABLE_DONT_CARE 0xd0 |
| 60 | #define CHIP_EN_DONT_CARE__FLAG 0x01 |
| 61 | |
| 62 | #define ECC_ENABLE 0xe0 |
| 63 | #define ECC_ENABLE__FLAG 0x0001 |
| 64 | |
| 65 | #define GLOBAL_INT_ENABLE 0xf0 |
| 66 | #define GLOBAL_INT_EN_FLAG 0x01 |
| 67 | |
| 68 | #define WE_2_RE 0x100 |
| 69 | #define WE_2_RE__VALUE 0x003f |
| 70 | |
| 71 | #define ADDR_2_DATA 0x110 |
| 72 | #define ADDR_2_DATA__VALUE 0x003f |
| 73 | |
| 74 | #define RE_2_WE 0x120 |
| 75 | #define RE_2_WE__VALUE 0x003f |
| 76 | |
| 77 | #define ACC_CLKS 0x130 |
| 78 | #define ACC_CLKS__VALUE 0x000f |
| 79 | |
| 80 | #define NUMBER_OF_PLANES 0x140 |
| 81 | #define NUMBER_OF_PLANES__VALUE 0x0007 |
| 82 | |
| 83 | #define PAGES_PER_BLOCK 0x150 |
| 84 | #define PAGES_PER_BLOCK__VALUE 0xffff |
| 85 | |
| 86 | #define DEVICE_WIDTH 0x160 |
| 87 | #define DEVICE_WIDTH__VALUE 0x0003 |
| 88 | |
| 89 | #define DEVICE_MAIN_AREA_SIZE 0x170 |
| 90 | #define DEVICE_MAIN_AREA_SIZE__VALUE 0xffff |
| 91 | |
| 92 | #define DEVICE_SPARE_AREA_SIZE 0x180 |
| 93 | #define DEVICE_SPARE_AREA_SIZE__VALUE 0xffff |
| 94 | |
| 95 | #define TWO_ROW_ADDR_CYCLES 0x190 |
| 96 | #define TWO_ROW_ADDR_CYCLES__FLAG 0x0001 |
| 97 | |
| 98 | #define MULTIPLANE_ADDR_RESTRICT 0x1a0 |
| 99 | #define MULTIPLANE_ADDR_RESTRICT__FLAG 0x0001 |
| 100 | |
| 101 | #define ECC_CORRECTION 0x1b0 |
| 102 | #define ECC_CORRECTION__VALUE 0x001f |
| 103 | |
| 104 | #define READ_MODE 0x1c0 |
| 105 | #define READ_MODE__VALUE 0x000f |
| 106 | |
| 107 | #define WRITE_MODE 0x1d0 |
| 108 | #define WRITE_MODE__VALUE 0x000f |
| 109 | |
| 110 | #define COPYBACK_MODE 0x1e0 |
| 111 | #define COPYBACK_MODE__VALUE 0x000f |
| 112 | |
| 113 | #define RDWR_EN_LO_CNT 0x1f0 |
| 114 | #define RDWR_EN_LO_CNT__VALUE 0x001f |
| 115 | |
| 116 | #define RDWR_EN_HI_CNT 0x200 |
| 117 | #define RDWR_EN_HI_CNT__VALUE 0x001f |
| 118 | |
| 119 | #define MAX_RD_DELAY 0x210 |
| 120 | #define MAX_RD_DELAY__VALUE 0x000f |
| 121 | |
| 122 | #define CS_SETUP_CNT 0x220 |
| 123 | #define CS_SETUP_CNT__VALUE 0x001f |
| 124 | |
| 125 | #define SPARE_AREA_SKIP_BYTES 0x230 |
| 126 | #define SPARE_AREA_SKIP_BYTES__VALUE 0x003f |
| 127 | |
| 128 | #define SPARE_AREA_MARKER 0x240 |
| 129 | #define SPARE_AREA_MARKER__VALUE 0xffff |
| 130 | |
| 131 | #define DEVICES_CONNECTED 0x250 |
| 132 | #define DEVICES_CONNECTED__VALUE 0x0007 |
| 133 | |
| 134 | #define DIE_MASK 0x260 |
| 135 | #define DIE_MASK__VALUE 0x00ff |
| 136 | |
| 137 | #define FIRST_BLOCK_OF_NEXT_PLANE 0x270 |
| 138 | #define FIRST_BLOCK_OF_NEXT_PLANE__VALUE 0xffff |
| 139 | |
| 140 | #define WRITE_PROTECT 0x280 |
| 141 | #define WRITE_PROTECT__FLAG 0x0001 |
| 142 | |
| 143 | #define RE_2_RE 0x290 |
| 144 | #define RE_2_RE__VALUE 0x003f |
| 145 | |
| 146 | #define MANUFACTURER_ID 0x300 |
| 147 | #define MANUFACTURER_ID__VALUE 0x00ff |
| 148 | |
| 149 | #define DEVICE_ID 0x310 |
| 150 | #define DEVICE_ID__VALUE 0x00ff |
| 151 | |
| 152 | #define DEVICE_PARAM_0 0x320 |
| 153 | #define DEVICE_PARAM_0__VALUE 0x00ff |
| 154 | |
| 155 | #define DEVICE_PARAM_1 0x330 |
| 156 | #define DEVICE_PARAM_1__VALUE 0x00ff |
| 157 | |
| 158 | #define DEVICE_PARAM_2 0x340 |
| 159 | #define DEVICE_PARAM_2__VALUE 0x00ff |
| 160 | |
| 161 | #define LOGICAL_PAGE_DATA_SIZE 0x350 |
| 162 | #define LOGICAL_PAGE_DATA_SIZE__VALUE 0xffff |
| 163 | |
| 164 | #define LOGICAL_PAGE_SPARE_SIZE 0x360 |
| 165 | #define LOGICAL_PAGE_SPARE_SIZE__VALUE 0xffff |
| 166 | |
| 167 | #define REVISION 0x370 |
| 168 | #define REVISION__VALUE 0xffff |
Graham Moore | 15305c2 | 2016-03-24 22:14:35 +0900 | [diff] [blame] | 169 | #define MAKE_COMPARABLE_REVISION(x) swab16((x) & REVISION__VALUE) |
| 170 | #define REVISION_5_1 0x00000501 |
Chin Liang See | 3eb3e72 | 2014-09-12 00:42:17 -0500 | [diff] [blame] | 171 | |
| 172 | #define ONFI_DEVICE_FEATURES 0x380 |
| 173 | #define ONFI_DEVICE_FEATURES__VALUE 0x003f |
| 174 | |
| 175 | #define ONFI_OPTIONAL_COMMANDS 0x390 |
| 176 | #define ONFI_OPTIONAL_COMMANDS__VALUE 0x003f |
| 177 | |
| 178 | #define ONFI_TIMING_MODE 0x3a0 |
| 179 | #define ONFI_TIMING_MODE__VALUE 0x003f |
| 180 | |
| 181 | #define ONFI_PGM_CACHE_TIMING_MODE 0x3b0 |
| 182 | #define ONFI_PGM_CACHE_TIMING_MODE__VALUE 0x003f |
| 183 | |
| 184 | #define ONFI_DEVICE_NO_OF_LUNS 0x3c0 |
| 185 | #define ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS 0x00ff |
| 186 | #define ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE 0x0100 |
| 187 | |
| 188 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L 0x3d0 |
| 189 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE 0xffff |
| 190 | |
| 191 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U 0x3e0 |
| 192 | #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE 0xffff |
| 193 | |
| 194 | #define FEATURES 0x3f0 |
| 195 | #define FEATURES__N_BANKS 0x0003 |
| 196 | #define FEATURES__ECC_MAX_ERR 0x003c |
| 197 | #define FEATURES__DMA 0x0040 |
| 198 | #define FEATURES__CMD_DMA 0x0080 |
| 199 | #define FEATURES__PARTITION 0x0100 |
| 200 | #define FEATURES__XDMA_SIDEBAND 0x0200 |
| 201 | #define FEATURES__GPREG 0x0400 |
| 202 | #define FEATURES__INDEX_ADDR 0x0800 |
| 203 | |
| 204 | #define TRANSFER_MODE 0x400 |
| 205 | #define TRANSFER_MODE__VALUE 0x0003 |
| 206 | |
| 207 | #define INTR_STATUS(__bank) (0x410 + ((__bank) * 0x50)) |
| 208 | #define INTR_EN(__bank) (0x420 + ((__bank) * 0x50)) |
| 209 | |
| 210 | /* |
| 211 | * Some versions of the IP have the ECC fixup handled in hardware. In this |
| 212 | * configuration we only get interrupted when the error is uncorrectable. |
| 213 | * Unfortunately this bit replaces INTR_STATUS__ECC_TRANSACTION_DONE from the |
| 214 | * old IP. |
| 215 | */ |
| 216 | #define INTR_STATUS__ECC_UNCOR_ERR 0x0001 |
| 217 | #define INTR_STATUS__ECC_TRANSACTION_DONE 0x0001 |
| 218 | #define INTR_STATUS__ECC_ERR 0x0002 |
| 219 | #define INTR_STATUS__DMA_CMD_COMP 0x0004 |
| 220 | #define INTR_STATUS__TIME_OUT 0x0008 |
| 221 | #define INTR_STATUS__PROGRAM_FAIL 0x0010 |
| 222 | #define INTR_STATUS__ERASE_FAIL 0x0020 |
| 223 | #define INTR_STATUS__LOAD_COMP 0x0040 |
| 224 | #define INTR_STATUS__PROGRAM_COMP 0x0080 |
| 225 | #define INTR_STATUS__ERASE_COMP 0x0100 |
| 226 | #define INTR_STATUS__PIPE_CPYBCK_CMD_COMP 0x0200 |
| 227 | #define INTR_STATUS__LOCKED_BLK 0x0400 |
| 228 | #define INTR_STATUS__UNSUP_CMD 0x0800 |
| 229 | #define INTR_STATUS__INT_ACT 0x1000 |
| 230 | #define INTR_STATUS__RST_COMP 0x2000 |
| 231 | #define INTR_STATUS__PIPE_CMD_ERR 0x4000 |
| 232 | #define INTR_STATUS__PAGE_XFER_INC 0x8000 |
| 233 | |
| 234 | #define INTR_EN__ECC_TRANSACTION_DONE 0x0001 |
| 235 | #define INTR_EN__ECC_ERR 0x0002 |
| 236 | #define INTR_EN__DMA_CMD_COMP 0x0004 |
| 237 | #define INTR_EN__TIME_OUT 0x0008 |
| 238 | #define INTR_EN__PROGRAM_FAIL 0x0010 |
| 239 | #define INTR_EN__ERASE_FAIL 0x0020 |
| 240 | #define INTR_EN__LOAD_COMP 0x0040 |
| 241 | #define INTR_EN__PROGRAM_COMP 0x0080 |
| 242 | #define INTR_EN__ERASE_COMP 0x0100 |
| 243 | #define INTR_EN__PIPE_CPYBCK_CMD_COMP 0x0200 |
| 244 | #define INTR_EN__LOCKED_BLK 0x0400 |
| 245 | #define INTR_EN__UNSUP_CMD 0x0800 |
| 246 | #define INTR_EN__INT_ACT 0x1000 |
| 247 | #define INTR_EN__RST_COMP 0x2000 |
| 248 | #define INTR_EN__PIPE_CMD_ERR 0x4000 |
| 249 | #define INTR_EN__PAGE_XFER_INC 0x8000 |
| 250 | |
| 251 | #define PAGE_CNT(__bank) (0x430 + ((__bank) * 0x50)) |
| 252 | #define ERR_PAGE_ADDR(__bank) (0x440 + ((__bank) * 0x50)) |
| 253 | #define ERR_BLOCK_ADDR(__bank) (0x450 + ((__bank) * 0x50)) |
| 254 | |
| 255 | #define DATA_INTR 0x550 |
| 256 | #define DATA_INTR__WRITE_SPACE_AV 0x0001 |
| 257 | #define DATA_INTR__READ_DATA_AV 0x0002 |
| 258 | |
| 259 | #define DATA_INTR_EN 0x560 |
| 260 | #define DATA_INTR_EN__WRITE_SPACE_AV 0x0001 |
| 261 | #define DATA_INTR_EN__READ_DATA_AV 0x0002 |
| 262 | |
| 263 | #define GPREG_0 0x570 |
| 264 | #define GPREG_0__VALUE 0xffff |
| 265 | |
| 266 | #define GPREG_1 0x580 |
| 267 | #define GPREG_1__VALUE 0xffff |
| 268 | |
| 269 | #define GPREG_2 0x590 |
| 270 | #define GPREG_2__VALUE 0xffff |
| 271 | |
| 272 | #define GPREG_3 0x5a0 |
| 273 | #define GPREG_3__VALUE 0xffff |
| 274 | |
| 275 | #define ECC_THRESHOLD 0x600 |
| 276 | #define ECC_THRESHOLD__VALUE 0x03ff |
| 277 | |
| 278 | #define ECC_ERROR_BLOCK_ADDRESS 0x610 |
| 279 | #define ECC_ERROR_BLOCK_ADDRESS__VALUE 0xffff |
| 280 | |
| 281 | #define ECC_ERROR_PAGE_ADDRESS 0x620 |
| 282 | #define ECC_ERROR_PAGE_ADDRESS__VALUE 0x0fff |
| 283 | #define ECC_ERROR_PAGE_ADDRESS__BANK 0xf000 |
| 284 | |
| 285 | #define ECC_ERROR_ADDRESS 0x630 |
| 286 | #define ECC_ERROR_ADDRESS__OFFSET 0x0fff |
| 287 | #define ECC_ERROR_ADDRESS__SECTOR_NR 0xf000 |
| 288 | |
| 289 | #define ERR_CORRECTION_INFO 0x640 |
| 290 | #define ERR_CORRECTION_INFO__BYTEMASK 0x00ff |
| 291 | #define ERR_CORRECTION_INFO__DEVICE_NR 0x0f00 |
| 292 | #define ERR_CORRECTION_INFO__ERROR_TYPE 0x4000 |
| 293 | #define ERR_CORRECTION_INFO__LAST_ERR_INFO 0x8000 |
| 294 | |
| 295 | #define DMA_ENABLE 0x700 |
| 296 | #define DMA_ENABLE__FLAG 0x0001 |
| 297 | |
| 298 | #define IGNORE_ECC_DONE 0x710 |
| 299 | #define IGNORE_ECC_DONE__FLAG 0x0001 |
| 300 | |
| 301 | #define DMA_INTR 0x720 |
| 302 | #define DMA_INTR__TARGET_ERROR 0x0001 |
| 303 | #define DMA_INTR__DESC_COMP_CHANNEL0 0x0002 |
| 304 | #define DMA_INTR__DESC_COMP_CHANNEL1 0x0004 |
| 305 | #define DMA_INTR__DESC_COMP_CHANNEL2 0x0008 |
| 306 | #define DMA_INTR__DESC_COMP_CHANNEL3 0x0010 |
| 307 | #define DMA_INTR__MEMCOPY_DESC_COMP 0x0020 |
| 308 | |
| 309 | #define DMA_INTR_EN 0x730 |
| 310 | #define DMA_INTR_EN__TARGET_ERROR 0x0001 |
| 311 | #define DMA_INTR_EN__DESC_COMP_CHANNEL0 0x0002 |
| 312 | #define DMA_INTR_EN__DESC_COMP_CHANNEL1 0x0004 |
| 313 | #define DMA_INTR_EN__DESC_COMP_CHANNEL2 0x0008 |
| 314 | #define DMA_INTR_EN__DESC_COMP_CHANNEL3 0x0010 |
| 315 | #define DMA_INTR_EN__MEMCOPY_DESC_COMP 0x0020 |
| 316 | |
| 317 | #define TARGET_ERR_ADDR_LO 0x740 |
| 318 | #define TARGET_ERR_ADDR_LO__VALUE 0xffff |
| 319 | |
| 320 | #define TARGET_ERR_ADDR_HI 0x750 |
| 321 | #define TARGET_ERR_ADDR_HI__VALUE 0xffff |
| 322 | |
| 323 | #define CHNL_ACTIVE 0x760 |
| 324 | #define CHNL_ACTIVE__CHANNEL0 0x0001 |
| 325 | #define CHNL_ACTIVE__CHANNEL1 0x0002 |
| 326 | #define CHNL_ACTIVE__CHANNEL2 0x0004 |
| 327 | #define CHNL_ACTIVE__CHANNEL3 0x0008 |
| 328 | |
| 329 | #define ACTIVE_SRC_ID 0x800 |
| 330 | #define ACTIVE_SRC_ID__VALUE 0x00ff |
| 331 | |
| 332 | #define PTN_INTR 0x810 |
| 333 | #define PTN_INTR__CONFIG_ERROR 0x0001 |
| 334 | #define PTN_INTR__ACCESS_ERROR_BANK0 0x0002 |
| 335 | #define PTN_INTR__ACCESS_ERROR_BANK1 0x0004 |
| 336 | #define PTN_INTR__ACCESS_ERROR_BANK2 0x0008 |
| 337 | #define PTN_INTR__ACCESS_ERROR_BANK3 0x0010 |
| 338 | #define PTN_INTR__REG_ACCESS_ERROR 0x0020 |
| 339 | |
| 340 | #define PTN_INTR_EN 0x820 |
| 341 | #define PTN_INTR_EN__CONFIG_ERROR 0x0001 |
| 342 | #define PTN_INTR_EN__ACCESS_ERROR_BANK0 0x0002 |
| 343 | #define PTN_INTR_EN__ACCESS_ERROR_BANK1 0x0004 |
| 344 | #define PTN_INTR_EN__ACCESS_ERROR_BANK2 0x0008 |
| 345 | #define PTN_INTR_EN__ACCESS_ERROR_BANK3 0x0010 |
| 346 | #define PTN_INTR_EN__REG_ACCESS_ERROR 0x0020 |
| 347 | |
| 348 | #define PERM_SRC_ID(__bank) (0x830 + ((__bank) * 0x40)) |
| 349 | #define PERM_SRC_ID__SRCID 0x00ff |
| 350 | #define PERM_SRC_ID__DIRECT_ACCESS_ACTIVE 0x0800 |
| 351 | #define PERM_SRC_ID__WRITE_ACTIVE 0x2000 |
| 352 | #define PERM_SRC_ID__READ_ACTIVE 0x4000 |
| 353 | #define PERM_SRC_ID__PARTITION_VALID 0x8000 |
| 354 | |
| 355 | #define MIN_BLK_ADDR(__bank) (0x840 + ((__bank) * 0x40)) |
| 356 | #define MIN_BLK_ADDR__VALUE 0xffff |
| 357 | |
| 358 | #define MAX_BLK_ADDR(__bank) (0x850 + ((__bank) * 0x40)) |
| 359 | #define MAX_BLK_ADDR__VALUE 0xffff |
| 360 | |
| 361 | #define MIN_MAX_BANK(__bank) (0x860 + ((__bank) * 0x40)) |
| 362 | #define MIN_MAX_BANK__MIN_VALUE 0x0003 |
| 363 | #define MIN_MAX_BANK__MAX_VALUE 0x000c |
| 364 | |
| 365 | /* lld.h */ |
| 366 | #define GOOD_BLOCK 0 |
| 367 | #define DEFECTIVE_BLOCK 1 |
| 368 | #define READ_ERROR 2 |
| 369 | |
| 370 | #define CLK_X 5 |
| 371 | #define CLK_MULTI 4 |
| 372 | |
| 373 | /* spectraswconfig.h */ |
| 374 | #define CMD_DMA 0 |
| 375 | |
| 376 | #define SPECTRA_PARTITION_ID 0 |
| 377 | /**** Block Table and Reserved Block Parameters *****/ |
| 378 | #define SPECTRA_START_BLOCK 3 |
| 379 | #define NUM_FREE_BLOCKS_GATE 30 |
| 380 | |
| 381 | /* KBV - Updated to LNW scratch register address */ |
| 382 | #define SCRATCH_REG_ADDR CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR |
| 383 | #define SCRATCH_REG_SIZE 64 |
| 384 | |
| 385 | #define GLOB_HWCTL_DEFAULT_BLKS 2048 |
| 386 | |
| 387 | #define CUSTOM_CONF_PARAMS 0 |
| 388 | |
Chin Liang See | 3eb3e72 | 2014-09-12 00:42:17 -0500 | [diff] [blame] | 389 | #define INDEX_CTRL_REG 0x0 |
| 390 | #define INDEX_DATA_REG 0x10 |
| 391 | |
| 392 | #define MODE_00 0x00000000 |
| 393 | #define MODE_01 0x04000000 |
| 394 | #define MODE_10 0x08000000 |
| 395 | #define MODE_11 0x0C000000 |
| 396 | |
| 397 | |
| 398 | #define DATA_TRANSFER_MODE 0 |
| 399 | #define PROTECTION_PER_BLOCK 1 |
| 400 | #define LOAD_WAIT_COUNT 2 |
| 401 | #define PROGRAM_WAIT_COUNT 3 |
| 402 | #define ERASE_WAIT_COUNT 4 |
| 403 | #define INT_MONITOR_CYCLE_COUNT 5 |
| 404 | #define READ_BUSY_PIN_ENABLED 6 |
| 405 | #define MULTIPLANE_OPERATION_SUPPORT 7 |
| 406 | #define PRE_FETCH_MODE 8 |
| 407 | #define CE_DONT_CARE_SUPPORT 9 |
| 408 | #define COPYBACK_SUPPORT 10 |
| 409 | #define CACHE_WRITE_SUPPORT 11 |
| 410 | #define CACHE_READ_SUPPORT 12 |
| 411 | #define NUM_PAGES_IN_BLOCK 13 |
| 412 | #define ECC_ENABLE_SELECT 14 |
| 413 | #define WRITE_ENABLE_2_READ_ENABLE 15 |
| 414 | #define ADDRESS_2_DATA 16 |
| 415 | #define READ_ENABLE_2_WRITE_ENABLE 17 |
| 416 | #define TWO_ROW_ADDRESS_CYCLES 18 |
| 417 | #define MULTIPLANE_ADDRESS_RESTRICT 19 |
| 418 | #define ACC_CLOCKS 20 |
| 419 | #define READ_WRITE_ENABLE_LOW_COUNT 21 |
| 420 | #define READ_WRITE_ENABLE_HIGH_COUNT 22 |
| 421 | |
| 422 | #define ECC_SECTOR_SIZE 512 |
| 423 | |
| 424 | #define DENALI_BUF_SIZE (NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) |
| 425 | |
| 426 | struct nand_buf { |
| 427 | int head; |
| 428 | int tail; |
| 429 | /* seprating dma_buf as buf can be used for status read purpose */ |
| 430 | uint8_t dma_buf[DENALI_BUF_SIZE] __aligned(64); |
| 431 | uint8_t buf[DENALI_BUF_SIZE]; |
| 432 | }; |
| 433 | |
| 434 | #define INTEL_CE4100 1 |
| 435 | #define INTEL_MRST 2 |
| 436 | #define DT 3 |
| 437 | |
| 438 | struct denali_nand_info { |
Masahiro Yamada | 65e4145 | 2014-11-13 20:31:50 +0900 | [diff] [blame] | 439 | struct nand_chip nand; |
Chin Liang See | 3eb3e72 | 2014-09-12 00:42:17 -0500 | [diff] [blame] | 440 | int flash_bank; /* currently selected chip */ |
| 441 | int status; |
| 442 | int platform; |
| 443 | struct nand_buf buf; |
| 444 | struct device *dev; |
| 445 | int total_used_banks; |
| 446 | uint32_t block; /* stored for future use */ |
| 447 | uint32_t page; |
| 448 | void __iomem *flash_reg; /* Mapped io reg base address */ |
| 449 | void __iomem *flash_mem; /* Mapped io reg base address */ |
| 450 | |
| 451 | /* elements used by ISR */ |
| 452 | /*struct completion complete;*/ |
| 453 | |
| 454 | uint32_t irq_status; |
| 455 | int irq_debug_array[32]; |
| 456 | int idx; |
| 457 | int irq; |
| 458 | |
| 459 | uint32_t devnum; /* represent how many nands connected */ |
| 460 | uint32_t fwblks; /* represent how many blocks FW used */ |
| 461 | uint32_t totalblks; |
| 462 | uint32_t blksperchip; |
| 463 | uint32_t bbtskipbytes; |
| 464 | uint32_t max_banks; |
| 465 | }; |
| 466 | |
Scott Wood | d396372 | 2015-06-26 19:03:26 -0500 | [diff] [blame] | 467 | #endif /* __DENALI_H__ */ |